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MPC9772 Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # MPC9772
Description  3.3V 1:12 LVCMOS PLL Clock Generator
PDF  18 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

MPC9772 Datasheet(HTML) 6 Page - Renesas Technology Corp

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REVISION 8 3/16/16
6
©2016 Integrated Device Technology, Inc.
MPC9772 DATA SHEET
Table 9. DC Characteristics (VCC = 3.3 V ± 5%, TA = -40° to 85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VCC_PLL
PLL Supply Voltage
3.0
VCC
V
LVCMOS
VIH
Input High Voltage
2.0
VCC + 0.3
V
LVCMOS
VIL
Input Low Voltage
0.8
V
LVCMOS
VOH
Output High Voltage
2.4
V
IOH = –24 mA
(1)
1. The MPC9772 is capable of driving 50
 transmission lines on the incident edge. Each output drives one 50  parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50  series terminated transmission lines.
VOL
Output Low Voltage
0.55
0.30
V
V
IOL = 24 mA
IOL = 12 mA
ZOUT
Output Impedance
14 – 17
IIN
Input Current(2)
2. Inputs have pull-down resistors affecting the input current.
200
A
VIN = VCC or
GND
ICC_PLL
Maximum PLL Supply Current
3.0
5.0
mA
VCC_PLL Pin
ICCQ
Maximum Quiescent Supply Current
15
mA
All VCC Pins
Table 10. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40° to +85°C)
(1), (2), continued on next page
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
TA = 0°C
to +70°C
TA = –40°C
to +85°C
fREF
Input reference frequency
4 feedback
6 feedback
8 feedback
10 feedback
12 feedback
16 feedback
20 feedback
24 feedback
32 feedback
40 feedback
Input reference frequency in PLL bypass mode(3)
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
15.0
12.0
250
115.00
76.67
57.50
46.00
38.33
28.75
23.00
19.16
14.37
11.50
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
PLL bypass
fVCO
VCO frequency range(4)
200
480
460
MHz
fXTAL
Crystal interface frequency range(4)
10
25
MHz
fMAX
Output Frequency
2 output
4 output
6 output
8 output
10 output
12 output
16 output
20 output
24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
230.00
115.00
76.67
57.50
46.00
38.33
28.75
23.00
19.16
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
fSTOP_CLK Serial interface clock frequency
20
MHz
tPW,MIN
Input Reference Pulse Width(5)
2.0
ns
tR, tF
CCLKx Input Rise/Fall Time(6)
1.0
ns
0.8 to 2.0 V



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