REVISION 8 3/16/16

14

©2016 Integrated Device Technology, Inc.

MPC9772 DATA SHEET

Figure 16. Output-to-Output Skew tSK(O)

Figure 17. Propagation Delay (t(), Static Phase

Offset) Test Reference

Figure 18. Output Duty Cycle (DC)

The pin-to-pin skew is defined as the worst case difference in

propagation delay between any similar delay path within a single

device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

VCC2

GND

VCC

VCC2

GND

tSK(O)

VCC

VCC2

GND

tP

T0

DC = tP/T0 x 100%

VCC

VCC2

GND

VCC

VCC2

GND

t()

CCLKx

FB_IN

TJIT() = |T0-T1mean|

CCLKx

FB_IN

The deviation in t0 for a controlled edge with respect to a t0 mean in a

random sample of cycles

Figure 19. I/O Jitter

TN

TJIT(CC) = |TN-TN+1|

TN+1

TJIT(PER) = |TN-1/f0|

T0

Figure 20. Cycle-to-Cycle Jitter

Figure 21. Period Jitter

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over a

random sample of cycles

tF

tR

VCC=3.3 V

2.4

0.55

Figure 22. Output Transition Time Test Reference