MPC9772 datasheet(9/18 Pages) RENESAS

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REVISION 8 3/16/16

MPC9772 DATA SHEET

MPC9772 Individual Output Disable

(Clock Stop) Circuitry

The individual clock stop (output enable) control of the

MPC9772 allows designers, under software control, to

implement power management into the clock distribution

design. A simple serial interface and a clock stop control logic

provides a mechanism through which the MPC9772 clock

outputs can be individually stopped in the logic ‘0’ state: The

clock stop mechanism allows serial loading of a 12-bit serial

input register. This register contains one programmable clock

stop bit for 12 of the 14 output clocks. The QC0 and QFB

outputs cannot be stopped (disabled) with the serial port.

The user can program an output clock to stop (disable) by

writing logic ‘0’ to the respective stop enable bit. Likewise, the

user may programmably enable an output clock by writing

logic ‘1’ to the respective enable bit. The clock stop logic

enables or disables clock outputs during the time when the

output would be in normally in logic low state, eliminating the

possibility of short or ‘runt’ clock pulses.

The user can write to the serial input register through the

STOP_DATA input by supplying a logic ‘0’ start bit followed

serially by 12 NRZ disable/enable bits. The period of each

STOP_DATA bit equals the period of the free—running

STOP_CLK signal. The STOP_DATA serial transmission

should be timed so the MPC9772 can sample each

STOP_DATA bit with the rising edge of the free—running

STOP_CLK signal. (See Figure 5.)

SYNC Output Description

The MPC9772 has a system synchronization pulse output

QSYNC. In configurations with the output frequency

relationships are not integer multiples of each other QSYNC

provides a signal for system synchronization purposes. The

MPC9772 monitors the relationship between the A bank and

the B bank of outputs. The QSYNC output is asserted (logic

low) one period in duration and one period prior to the

coincident rising edges of the QA and QC outputs. The

duration and the placement of the pulse is dependent QA and

QC output frequencies: the QSYNC pulse width is equal to

the period of the higher of the QA and QC output frequencies.

Figure 6 shows various waveforms for the QSYNC output.

The QSYNC output is defined for all possible combinations of

the bank A and bank C outputs.

Figure 3. Example Configuration

Figure 4. Example Configuration

MPC9772

fref = 33.3 MHz

33.3 MHz

100 MHz

33.3 MHz (Feedback)

200 MHz

CCLK0

VCO_SEL

FSEL_A[1:0]

FSEL_B[1:0]

FSEL_C[1:0]

FSEL_FB[2:0]

QA[3:0]

QB[3:0]

QC[3:0]

QFB

CCLK1

CCLK_SEL

FB_IN

101

MPC9772 example configuration (feedback of QFB = 33.3 MHz,

fVCO=400 MHz, VCO_SEL=1, M=12, NA=12, NB=4, NC=2).

Frequency Range

TA = 0°C to +70°C

TA = –40°C to +85°C

Input

16.6 – 40 MHz

16.6 – 38.33 MHz

QA Outputs

16.6 – 40 MHz

16.6 – 38.33 MHz

QA Outputs

50 – 120 MHz

50 – 115 MHz

QC Outputs

100 – 240 MHz

100 – 230 MHz

MPC9772

fref = 25 MHz

62.5 MHz

25 MHz (Feedback)

125 MHz

CCLK0

VCO_SEL

FSEL_A[1:0]

FSEL_B[1:0]

FSEL_C[1:0]

FSEL_FB[2:0]

QA[3:0]

QB[3:0]

QC[3:0]

QFB

CCLK1

CCLK_SEL

FB_IN

011

MPC9772 example configuration (feedback of QFB = 25 MHz,

fVCO=250 MHz, VCO_SEL=1, M=10, NA=4, NB=4, NC=2).

Frequency Range

TA = 0°C to +70°C TA = –40°C to +85°C

Input

20 – 48 MHz

20 – 46 MHz

QA Outputs

50 – 120 MHz

50 – 115 MHz

QA Outputs

50 – 120 MHz

50 – 115 MHz

QC Outputs

100 – 240 MHz

100 – 230 MHz

Figure 5. Clock Stop Circuit Programming

STOP_CLK

STOP_DATA

START

QA0

QA1

QA2

QA3

QB0

QB1

QB2

QB3

QC1

QC2

QC3

QSYNC

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