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DAC39RF10 Datasheet(PDF) 70 Page - Texas Instruments

Part # DAC39RF10
Description  DAC39RF10 10.24-GSPS, 16-bit, Dual and Single Channel, Multi-Nyquist Digital-to-Analog Converter (DAC) with JESD204B, C Interface
PDF  178 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

DAC39RF10 Datasheet(HTML) 70 Page - Texas Instruments

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Table 8-12. PLL Configuration Table for 8b/10b Encoding Modes (continued)
Rdecimal
(fraction)
DACCLK Range
(FDAC) (GHz)
Register Values to Program
Actual Frequency Multipliers
Lane Bit Rate
(Gbps)
REFDIV
MPY
RATE
VRANGE
REFDIV
MPY
RATE
1 (40/40)
1.5625-3.2
0x04
0x10
0x2
FDAC<2.17GHz
1/4
4
1
1.5625 – 3.2
1 (40/40)
3.125-6.4
0x08
0x10
0x1
FDAC<4.34GHz
1/8
4
2
3.125 – 6.4
1 (40/40)
6.25-12.8
0x10
0x10
0x0
FDAC<8.68GHz
1/16
4
4
6.25 – 12.8
1.25 (40/32)
0.625-1.28
0x02
0x14
0x3
FDAC<0.868GHz
1/2
5
0.5
0.78125 – 1.6
1.25 (40/32)
1.25-2.56
0x04
0x14
0x2
FDAC<1.736GHz
1/4
5
1
1.5625 – 3.2
1.25 (40/32)
2.5-5.12
0x08
0x14
0x1
FDAC<3.472GHz
1/8
5
2
3.125 – 6.4
1.25 (40/32)
5.0-10.24
0x10
0x14
0x0
FDAC<6.994GHz
1/16
5
4
6.25 – 12.8
1.667 (40/24)
0.47-0.96
0x03
0x28
0x3
FDAC<0.651GHz
1/3
10
0.5
0.78125 – 1.6
1.667 (40/24)
0.94-1.92
0x03
0x14
0x2
FDAC<1.302GHz
1/3
5
1
1.5625 – 3.2
1.667 (40/24)
1.88-3.84
0x06
0x14
0x1
FDAC<2.604GHz
1/6
5
2
3.125 – 6.4
1.667 (40/24)
3.75-7.68
0x0C
0x14
0x0
FDAC<5.208GHz
1/12
5
4
6.25 – 12.8
2 (40/20)
0.781-1.6
0x02
0x10
0x2
FDAC<1.085GHz
1/2
4
1
1.5625 – 3.2
2 (40/20)
1.5625-3.2
0x04
0x10
0x1
FDAC<2.17GHz
1/4
4
2
3.125 – 6.4
2 (40/20)
3.125-6.4
0x08
0x10
0x0
FDAC<4.34GHz
1/8
4
4
6.25 – 12.8
2.5 (40/16)
0.625-1.28
0x02
0x14
0x2
FDAC<0.868GHz
1/2
5
1
1.5625 – 3.2
2.5 (40/16)
1.25-2.56
0x04
0x14
0x1
FDAC<1.736GHz
1/4
5
2
3.125 – 6.4
2.5 (40/16)
2.5-5.12
0x08
0x14
0x0
FDAC<3.472GHz
1/8
5
4
6.25 – 12.8
3.3333 (40/12)
0.47 – 0.96
0x03
0x28
0x2
FDAC<0.651GHz
1/3
10
1
1.5625 – 3.2
3.3333 (40/12)
0.94 – 1.92
0x03
0x14
0x1
FDAC<1.302GHz
1/3
5
2
3.125 – 6.4
3.3333 (40/12)
1.88 – 3.84
0x06
0x14
0x0
FDAC<2.604GHz
1/6
5
4
6.25 – 12.8
4 (40/10)
0.781 – 1.6
0x02
0x10
0x1
FDAC<1.085GHz
1/2
4
2
3.125 – 6.4
4 (40/10)
1.5625 – 3.2
0x04
0x10
0x0
FDAC<2.17GHz
1/4
4
4
6.25 – 12.8
5 (40/8)
0.625-1.28
0x02
0x14
0x1
FDAC<0.868GHz
1/2
5
2
3.125 – 6.4
5 (40/8)
1.25-2.56
0x04
0x14
0x0
FDAC<1.736GHz
1/4
5
4
6.25 – 12.8
Table 8-13. PLL Configuration Table for 64b/66b Encoding Modes
RR decimal
(fraction)
DACCLK Range
(FDAC) (GHz)
Register Values to Program
Actual Frequency Multipliers
Lane Bit Rate (FBIT)
(Gbps)
REFDIV
MPY
RATE
VRANGE
REFDIV
MPY
RATE
0.515625 (33/64)
6.06 – 12.41
0x20
0x21
0x1
FDAC<8.417GHz
1/32
8.25
2
3.125 – 6.4
0.6875 (33/48)
4.55 – 9.31
0x18
0x21
0x1
FDAC<6.313GHz
1/24
8.25
2
3.125 – 6.4
0.6875 (33/48)
9.09 – 12.8
0x30
0x21
0x0
FDAC<12.625GHz
1/48
8.25
4
6.25 – 8.8
0.825 (33/40)
3.79 – 7.76
0x14
0x21
0x1
FDAC<5.261GHz
1/20
8.25
2
3.125 – 6.4
0.825 (33/40)
7.58 – 12.8
0x28
0x21
0x0
FDAC<10.521GHz
1/40
8.25
4
6.25 – 10.56
1.03125 (33/32)
3.03 – 6.21
0x10
0x21
0x1
FDAC<4.208GHz
1/16
8.25
2
3.125 – 6.4
1.03125 (33/32)
6.06 – 12.41
0x20
0x21
0x0
FDAC<8.417GHz
1/32
8.25
4
6.25 – 12.8
1.375 (33/24)
2.27 – 4.65
0x0C
0x21
0x1
FDAC<3.156GHz
1/12
8.25
2
3.125 – 6.4
1.375 (33/24)
4.55 – 9.31
0x18
0x21
0x0
FDAC<6.313GHz
1/24
8.25
4
6.25 – 12.8
1.65 (33/20)
1.89 – 3.88
0x0A
0x21
0x1
FDAC<2.630GHz
1/10
8.25
2
3.125 – 6.4
1.65 (33/20)
3.79 – 7.76
0x14
0x21
0x0
FDAC<5.261GHz
1/20
8.25
4
6.25 – 12.8
2.0625 (33/16)
1.52 – 3.10
0x08
0x21
0x1
FDAC<2.104GHz
1/8
8.25
2
3.125 – 6.4
2.0625 (33/16)
3.03 – 6.21
0x10
0x21
0x0
FDAC<4.208GHz
1/16
8.25
4
6.25 – 12.8
2.75 (33/12)
1.14 – 2.33
0x06
0x21
0x1
FDAC<1.578GHz
1/6
8.25
2
3.125 – 6.4
2.75 (33/12)
2.27 – 4.65
0x0C
0x21
0x0
FDAC<3.156GHz
1/12
8.25
4
6.25 – 12.8
3.3 (33/10)
0.95 – 1.94
0x05
0x21
0x1
FDAC<1.315GHz
1/5
8.25
2
3.125 – 6.4
3.3 (33/10)
1.89 – 3.88
0x0A
0x21
0x0
FDAC<2.630GHz
1/10
8.25
4
6.25 – 12.8
4.125 (33/8)
0.76 – 1.55
0x04
0x21
0x1
FDAC<1.052GHz
1/4
8.25
2
3.125 – 6.4
4.125 (33/8)
1.52 – 3.10
0x08
0x21
0x0
FDAC<2.104GHz
1/8
8.25
4
6.25 – 12.8
8.3.7.8 Serdes Crossbar
The device includes a crossbar immediately after coming out of the PHY that allows mapping of signals between
lanes to simplify PCB routing between the Tx and Rx which could save PCB complexity or shorten the traces
(reduce loss). See LANE_SEL n.
DAC39RF10
SBASAC8 – MAY 2023
www.ti.com
70
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Product Folder Links: DAC39RF10



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