105 Hardware Specifications

3

Preliminary/Subject to Change without Notice

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PCI interface

— Compliant with PCI Local Bus Specification, Revision 2.0

— Supports PCI interlocked accesses to memory using LOCK signal and protocol

— Supports accesses to all PCI address spaces

— Selectable big- or little-endian operation

— Store gathering on PCI writes to memory

— Selectable memory prefetching of PCI read accesses

— Only one external load presented by the MPC105 to the PCI bus

— PCI configuration registers

— Interface operates at 16–33 MHz

— Data buffering (in/out)

— Parity supported

— 3.3 V/5.0 V compatible

•

Concurrent transactions on 60x and PCI buses supported

•

Memory interface

— Programmable timing supported

— Supports either DRAM or SDRAM

— High bandwidth (64-bit) data bus

— Supports self-refreshing DRAM in sleep and suspend modes

— Supports 1 to 8 banks built of x1, x4, x8, x9, x16, or x18 DRAMs

— Supports PowerPC reference platform-compliant contiguous or discontiguous memory maps

— 1 Gbyte of RAM space, 16 Mbytes of ROM space

— Supports 8-bit asynchronous ROM or 32-/64-bit burst-mode ROM

— Supports writing to Flash ROM

— Configurable external buffer control logic

— Parity supported

— TTL compatible

•

Power management

— Fully-static 3.3 V CMOS design

— Supports 60x nap, doze, and sleep power management modes, and suspend mode

•

IEEE 1149.1-compliant, JTAG boundary-scan interface

•

304-pin ball grid array (BGA) package

1.2 General Parameters

The following list provides a summary of the general parameters of the MPC105.

Technology

0.5

µm CMOS, four-layer metal

Chip size

6.69 mm x 5.82 mm (38.9 mm2)

Chip performance

25 MHz, 33.33 MHz, 50 MHz, and 66.67 MHz

Package

Surface mount 304-pin C4 ceramic ball grid array (CBGA)

Power supplies

3.3 V

± 5%

Maximum input rating

5.0 V

± 10%

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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