AD9460

Rev. 0 | Page 31 of 32

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD

0.27

0.22

0.17

1

25

26

50

76

100

75

51

14.00 BSC SQ

16.00 BSC SQ

0.50 BSC

LEAD PITCH

0.75

0.60

0.45

1.20

MAX

1

25

26

50

76

100

75

51

1.05

1.00

0.95

0.20

0.09

0.08 MAX

COPLANARITY

VIEW A

SEATING

PLANE

0° MIN

7°

3.5°

0°

0.15

0.05

VIEW A

PIN 1

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

9.50 SQ

EXPOSED

PAD

NOTES

1. CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED.

2. THE PACKAGE HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF

THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF

THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL

TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE

SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE

DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.

Figure 54. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-100-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

AD9460BSVZ-801

–40°C to +85°C

100-Lead TQFP_EP

SV-100-3

AD9460BSVZ-1051

–40°C to +85°C

100-Lead TQFP_EP

SV-100-3

AD9460-80LVDS/PCB

AD9460-80LVDS Mode Evaluation Board

AD9460-105LVDS/PCB

AD9460-105LVDS Mode Evaluation Board