CS5920 datasheet(134/160 Pages) AMCC

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S5920 – PCI Product

Revision 1.01 – November 28, 2005

AMCC Confidential and Proprietary

DS1596

134

Data Book

In Active mode, wait states can also be programmed.

This enables easier interfacing to slow Add-On logic

whichcannot transferdataatthe fullADCLKspeed.The

S5920 inserts a turnaround cycle after the address

phase for PCI Read cycles. If one or more wait states

have been programmed, the turnaround cycle is con-

sidered the first wait state of the first data phase of that

transaction.

For all Active mode transfers, the DXFR# signal is

used by Add-On logic as the data transfer signal. Data

must be latched at the rising edge of ADCLK when

DXFR# is asserted for a PCI write. Conversely, for PCI

Reads, the rising edge of ADCLK when DXFR# is

asserted can be used to increment to the next data

field.

Figure 71. Active mode PCI Read (Zero Programmed

Wait States) with PTADR#

Figure 72. Active Mode PCI Read without PTADR#

The PTADR# signal is controlled by the most signifi-

cant bit of every region control field in the PTCR

driven at the start of an Active mode transfer. If this bit

is set to one, the PTADR# pin will be enabled and

driven active (low) for one and only one clock after

PTATN# was sampled active provided PTWAIT# was

also sampled high.

Table 57. Big Endian conversion for a 16-bit bus. The

S5920 drives D[15:0] only

Transfer

Byte #

PCI Byte

Lane

Add-On Bus

Byte Lane

1st XFER

D7-D0

D15-D8

1st XFER

D15-D8

D7-D0

2nd XFER

D23-D16

D15-D8

2nd XFER

D31-D24

D7-D0

Table 58. Big Endian conversion for an 8-bit bus. The

S5920 drives D[7:0] only

Transfer

Byte #

PCI Byte

Lane

Add-On Bus

Byte Lane

1st XFER

D7-D0

2nd XFER

D15-D8

D7-D0

3rd XFER

D23-D16

D7-D0

4th XFER

D31-D24

D7-D0

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]

DXFR#

DQ[31:0]

PTWAIT#

PTADDR

DATA

PTADR#

01b

ADCLK

PTATN#

PTBURST#

PTNUM[1:0]

PTWR

PTBE[3:0]

DXFR#

DQ[31:0]

PTWAIT#

DATA

PTADR#

01b

234

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