AD9957 datasheet(4/38 Pages) AD

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AD9957

PRELIMINARY TECHNICAL DATA

Rev. PrF | Page 4 of 38

Parameter

Min

Typ

Max

Unit

NOISE SPECTRAL DENSITY (NSD) Continued

Eight Tone, 500KHz Tone Spacing

fout = 50 MHz

TBD

dBm / Hz

fout = 104 MHz

TBD

dBm / Hz

fout = 209 MHz

TBD

dBm / Hz

fout = 315 Mhz

TBD

dBm / Hz

fout = 403 MHz

TBD

dBm / Hz

MODULATOR CHARACTERISTICS (260MHz AOUT

Input Data: 10MS/s, QPSK, 4x Oversampled

I/Q Offset

Error Vector Magnitude

0.4

Input Data: 10MS/s GMSK 4x Oversampled

I/Q Offset

TBD

Error Vector Magnitude

TBD

Input Data: 10MS/s 256-QAM 4x Oversampled

I/Q Offset

TBD

Error Vector Magnitude

TBD

Adjacent Channel Leakage Ratio (ACLR)

WCDMA with 3.84MHz BW, 5MHz Channel Spacing

fDAC=1GSPS, fOUT=200MHz

fDAC=1GSPS, fOUT=400MHz

TIMING CHARACTERISTICS

Parallel Data Bus

Maximum Frequency

250

MS/s

Minimum TxEnable Pulse Width Low

Minimum TxEnable Pulse Width High

Minimum Data Setup Time (TxEnable to PDClk)

Minium Data Hold Time (PDClk rising edge to data change)

Serial Control Bus

Maximum Frequency

Mbps

Minimum Clock Pulse Width Low

Minimum Clock Pulse Width High

Maximum Clock Rise/Fall Time

Minimum Data Setup Time DVDD_I/O = 3.3 V

Minimum Data Hold Time

Maximum Data Valid Time

Wake-Up Time2

Minimum Reset Pulse Width High

SYSCLK Cycles3

I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V

I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time

Latency

I/O UPDATE to Frequency Change Propagation Delay

SYSCLK Cycles

I/O UPDATE to Phase Offset Change Propagation Delay

SYSCLK Cycles

I/O UPDATE to Amplitude Change Propagation Delay

SYSCLK Cycles

CMOS LOGIC INPUTS

Logic 1 Voltage

2.2

Logic 0 Voltage

0.8

Logic 1 Current

μA

Logic 0 Current

μA

Input Capacitance

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