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AD9957

PRELIMINARY TECHNICAL DATA

Rev. PrF | Page 16 of 38

two outputs. The use of balanced outputs reduces the amount of

common-mode noise at the DAC output, increasing signal-to-

noise ratio. An external resistor (RSET) connected between the

DAC_RSET pin and the DAC ground (AGND_DAC) establishes

a reference current. The full-scale output current of the DAC

(IOUT) is produced as a scaled version of the reference current

(see the Auxiliary DAC section that follows).

Proper attention should be paid to the load termination to keep the

output voltage within the specified compliance range, as voltages

developed beyond this range will cause excessive distortion and

might even damage the DAC output circuitry.

Auxiliary DAC

The full scale output current of the main DAC (IOUT) is con-

trolled by an 8-bit auxiliary DAC. An 8-bit code word stored in

the appropriate register map location sets IOUT according to the

following equation:

⎟

⎠

⎞

⎜

⎝

⎛ +

CODE

SET

OUT

(6)

Where RSET is the value of the RSET resistor (in ohms) and CODE

is the 8-bit value supplied to the auxiliary DAC (default is 127).

For example, with RSET=10,000 and CODE=127, then

IOUT=20.07mA.

INTERPOLATING DAC MODE

A block diagram of the AD9957 operating in the interpolating

DAC mode is shown in Figure 11; grayed out items are inactive.

In this mode, the Q data path, DDS and modulator are all dis-

abled; only the I data path is active.

CCI

(1x -63x)

DDS

cos(

ωt+θ)

sin(

ωt+θ)

DAC

(14-b)

Halfband

Filters

(4x)

Parallel Data

Timing &

Control

I/Q In

Internal Clock Timing & Control

PDClk

Clock

Multiplier

RefClk

Halfband

Filters

(4x)

Inv.

CCI

Inv.

CCI

DAC

Rset

Iout

AD9957: Interpolating DAC Mode

sin(x)

TxEn

OSF

AUX

DAC

(8-b)

DAC

Gain

Serial I/O

Port

Programming

Registers

RAM

Power

Down

Control

I Q

FTW

Freq.

Ramp

Logic

CCI

(1x -63x)

Figure 11: Interpolating DAC Mode

As in the quadrature modulation mode, the PDCLK pin func-

tions as a clock which serves to synchronize the input of data to

the AD9957. The PDCLK rate is given below. Note that it oper-

ates at a rate that is half of that for the quadrature modulation

mode.

SYSCLK

DATA

(Interpolating DAC mode)

Because no modulation takes place, the spectrum of the data

supplied at the parallel port remains at base band. However, a

sample rate conversion takes place based on the programmed

interpolation rate. The interpolation hardware processes the

signal, by effectively performing an over-sample with zero-

stuffing operation. However, the original input spectrum re-

mains intact and the images that would otherwise occur from

the sample rate conversion process are suppressed by the inter-

polation signal chain.

The PDCLK pin is an output and serves as a data clock timing

source. The output clock rate is fDATA as explained in the Input

Data Assembler section. Each PDCLK rising edge latches a data

word into the I data path.

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