AD9957 datasheet(12/38 Pages) AD

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AD9957

PRELIMINARY TECHNICAL DATA

Rev. PrF | Page 12 of 38

DATA is shown in Figure 5 and Figure 6.

tDH

TxENABLE

PDCLK

D<13:0>

tDH

tDS

Figure 5. 18-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode

Table 3. Parallel Data Bus Timing

Symbol

Definition

Minimum

tDS

Data Setup Time

4 ns

tDH

Data Hold Time

0 ns

Figure 6: Dual Serial I/Q Bitstream Timing Diagram – BFI mode

Table 4: Serial Data Bus Timing

Symbol

Definition

Minimum

tDS

Data Setup Time

TBD

tDH

Data Hold Time

TBD

Input Data Assembler

The input to the AD9957 is an 18-bit parallel data port in quad-

rature modulation mode (or a dual serial data port in the BFI

mode). It is assumed that two consecutive 18-bit words repre-

sent the real (I) and imaginary (Q) parts of a complex number

that has the form I+jQ. The 18-bit words are supplied to the

input of the AD9957 at a rate of:

SYSCLK

DATA

(QDUC mode)

Where fSYSCLK is the sample rate of the DAC and R is the interpo-

lation factor of the programmable interpolation filter.

When device is programmed to operate in BFI mode, the 18-bit

parallel input is converted to a dual serial input. That is, one

pin is assigned as the serial input for the "I" words and one pin

is assigned as the serial input for the "Q" words. The other 16

pins are not used in the BFI mode. Furthermore, each I and Q

word has 16-bit resolution (as compared with 18-bit resolution

in the non-BFI mode). In BFI mode, fDATA is the bit rate of the I

and Q data streams and is given by:

SYSCLK

DATA =

(BFI mode)

Encoding and pulse shaping of symbols must be implemented

before the data is presented to the input of the AD9957. Data

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