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PRELIMINARY TECHNICAL DATA

AD9957

Rev. PrF | Page 33 of 38

CFR1<9> = 0 (default), disables Shaped On-Off Keying.

The clocks to this function are stopped for power sav-

ings.

CFR1<9> = 1, enables Shaped On-Off Keying.

CFR1<8> sets the mode of operation.

CFR1<8>

: Automatic Output Shaped Keying Enable

If CFR1<9> is clear, this bit is ignored.

CFR1<8> = 0 enables MANUAL Shaped On-Off Keying.

CFR1<8> = 1 enables AUTO Shaped On-Off Keying.

CFR1<7>

: Digital Power Down

CFR1<7> = 0 (default), enables the digital circuitry.

CFR1<7> = 1, disables the digital circuitry, putting it in

its’ lowest power dissipation state.

CFR1<6>

: DAC Power Down

CFR1<6> = 0 (default), enables the DAC Circuitry.

CFR1<6> = 1, disables the DAC Circuitry, putting it in a

low power dissipation state.

CFR1<5>

: Clock Input Power Down

CFR1<5> = 0 (default), enables the Clock Input Cir-

cuitry.

CFR1<5> = 1, disables the Clock Input Circuitry putting

it in a low power dissipation state.

CFR1<4>

: Open

CFR1<3>

: External Power Down Mode

When CFR1<3> = 0 (default) the external power down

mode selected is “fast recovery power down”. In this

mode, when the EXTPWRDWN input pin is high, the

digital logic and the DAC digital logic are powered

down. The DAC bias circuitry, comparator, PLL, oscilla-

tor, and clock input circuitry is NOT powered down.

When CFR1<3> = 1, the external power down mode se-

lected is “full power down”. In this mode, when the

EXTPWRDWN input pin is high, all functions are pow-

ered down including the DAC and PLL, which take a

significant amount of time to power up.

CFR1<2>: Automatic Power Down

CFR1<2> = 0 (default), disables automatic power down.

When CFR1<2> = 1 when TX ENABLE is de-asserted

for a sufficiently long period of time the device auto-

matically switches into its low power mode.

CFR1<1>: SDIO Input Only

CFR1<1> = 0 (default), configures the SDIO pin for bi-

directional operation (2-wire serial programming

mode).

CFR1<1> = 1, configures the serial data I/O pin (SDIO)

as an input only pin (3-wire serial programming mode).

CFR1<0>: LSB First

CFR1<0> = 0 (default), sets MSB first format.

CFR1<0> = 1, sets LSB first format.

Control Function Register #2 (CFR2)

CFR2<31>

: BlackFin Interface Mode Active bit.

When CFR2<31>= 0 (default), the parallel input data

port operates as described in the data assembler section

of this document.

When CFR2<31> = 1, the AD9957 data port is config-

ured for direct connection to the BlackFin SPORT inter-

face. See the BlackFin Interface section of this document

for details.

CFR2<30>

: BlackFin Bit Order bit.

This bit is ignored if the AD9957 is not operating in the

BlackFin Interface Mode (see CFR2<31>).

CFR2<30>

= 0 (default) sets MSB first format.

CFR2<30>

= 1 sets LSB first format.

CFR2<29>

: BlackFin Early Frame Sync Enable bit.

This bit is ignored if the AD9957 is not operating in the

BlackFin Interface Mode (see CFR2<31>).

When CFR2<29>= 0 (default), the frame sync signal is

expected by the AD9957 to be co-incident with the first

data bit transmitted. (‘Late frame sync operation’ in the

Blackfin documentation).

When CFR2<29> = 1, the frame sync signal is expected

by the AD9957 to be one cycle preceding the first data

bit transmitted. (‘Early frame sync operation’ in the

Blackfin documentation). Also, for continuous data

transmission, the early frame sync bit will be co-incident

with the last bit of the previous word transmitted.

CFR2<28:25>: Open

. Leave these bits clear

CFR2<24>

: Single Tone Profile Enable bit.

When CFR2<24>= 0 (default), direct modulation of

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