AD9957 datasheet(17/38 Pages) AD

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PRELIMINARY TECHNICAL DATA

AD9957

Rev. PrF | Page 17 of 38

The timing relationship between TxENABLE, PDCLK, and

DATA is shown in Figure 12.

tDH

TxENABLE

PDCLK

D<13:0>

IK– 1

tDH

tDS

Figure 12. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode

SINGLE-TONE MODE

DDS

cos(

ωt+θ)

sin(

ωt+θ)

DAC

(14-b)

Halfband

Filters

(4x)

Parallel Data

Timing &

Control

I/Q In

Internal Clock Timing & Control

PDClk

Clock

Multiplier

RefClk

Halfband

Filters

(4x)

Inv.

CCI

Inv.

CCI

DAC

Rset

Iout

AD9957: Single-Tone Mode

sin(x)

TxEn

AUX

DAC

(8-b)

DAC

Gain

Serial I/O

Port

Programming

Registers

RAM

Power

Down

Control

FTW

CCI

(1x -63x)

CCI

(1x - 63x)

Freq.

Ramp

Logic

Figure 13: Single-Tone Mode

A block diagram of the AD9957 operating in the single-tone

mode is shown in Figure 13; grayed out items are inactive. In

this mode, both I and Q data paths are disabled from the 18-bit

parallel data port up to and including the modulator. The in-

ternal DDS core produces a signal whose frequency depends on

the programmed tuning word. The user may select either the

cosine (default) or sine output of the DDS. The sinusoid at the

DDS output can be scaled via a 14-bit amplitude scale factor

(ASF) and optionally routed through the Inverse SINC filter.

Amplitude Scale Factor (ASF)

Output amplitude is controlled by a 14-bit digital multiplier

called the Amplitude Scale Factor (ASF), which is programmed

via the appropriate control registers. It is available for each of

the eight profiles. The LSB weight is 2–14, which yields a multi-

plier range of 0 to 1.99993896484375 (1-2-14).

In addition to the ability to generate single tone signals in this

mode, the AD9957 can also provide 2-, 4-, or 8-level modula-

tion of frequency, phase, or amplitude by means of the eight

available profile registers and the Profile<0:2> pins.

I/O_UPDATE Pin

In the single-tone mode, the I/O_UPDATE pin serves as a sig-

nal update strobe. Frequency, phase and amplitude control

words for the DDS are programmed via the serial port (see the

Control Register description). The serial port is an asynchro-

nous interface; the I/O_UPDATE pin allows for synchroniza-

tion of the AD9957 output with external circuitry when new

frequency, phase, or amplitude values are programmed into the

on-chip profile registers. A rising edge initiates transfer of the

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