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AD9957 Datasheet(PDF) 24 Page - Analog Devices

Part # AD9957
Description  1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC
PDF  38 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9957 Datasheet(HTML) 24 Page - Analog Devices

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AD9957
PRELIMINARY TECHNICAL DATA
Rev. PrF | Page 24 of 38
REGISTER MAP AND DESCRIPTIONS
REGISTER MAP
Register
Name (Serial
Address)
Bit
Range
Bit 7
(MSB)
Bit 6
Bit 5
Bit4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value OR
Profile
<31:24>
RAM
Enable
OPEN
RAM QDUC
Evaluation
OPEN
QDUC Operating Mode
00h
<23:16>
Manual
OSK
External
Control
Inverse Sinc
Filter Enable
Clear CCI
Internal Profile Control
Enable Sine
Output
00h
<15:8>
OPEN
Auto-Clear
Phase
Accum
OPEN
Clear Phase
Accum
Load ARR
@ I/O
update
Output
Shaped
Keying
Enable
Auto
Output
Shaped
Keying
00h
Control
Function
Register 1
CFR1
(00h)
<7:0>
Digital
Power
Down
DAC Power
Down
Clock
Input
Power
Down
Aux DAC
Power Down
External
Power
Down
Mode
Auto
Power
Down
Enable
SDIO Input
Only
LSB First
00h
<31:24>
BlackFin
Interface
Mode
Active
BlackFin Bit
Order
Black Fin
Early
Frame
Sync
Enable
OPEN
00h
<23:16>
Internal
IO
Update
Active
Enable IO
Update
Clock
OPEN
Read
Effective
FTW
40h
<15:8>
IO Update Rate Control
PDCLK
Rate
Control
Data Format
Enable
PDCLK
PDCLK
Clock
Invert
TxEnable
Invert
Q First Data
Pairing
08h
Control
Function
Register 2
(CFR2)
(01h)
<7:0>
Matched
Latency
Enable
Data
Assembler
Hold Last
Value
Sync
Sample
Error
Mask
OPEN
FM Gain
20h
<31:24>
DRV0<1:0>
OPEN
VCO SEL <2:0>
1Fh
<23:16>
OPEN
ICP<2:0>
OPEN
3Fh
<15:8>
REFCLK
Input
Divider
Disable
OPEN
PLL Enable
40h
Control
Function
Register 3
(CFR3)
(02h)
<7:0>
N:<6:0>
OPEN
00h
<31:24>
OPEN
00h
<23:16>
OPEN
00h
<15:8>
OPEN
00h
Auxilliary
DAC Control
Register
(03h)
<7:0>
FSC<7:0>
FFh



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