ADF7021

Preliminary Technical Data

Rev. PrI | Page 36 of 44

REGISTER 8—POWER DOWN TEST REGISTER

PD1

PD3

PD4

PD5

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2 (0) C1 (0)

CONTROL

BITS

DB1

DB0

C3 (0)

C4 (1)

Rx RESET

CR1

DB15

DB14

DB13

DB12

DB11

LE1

PD6

DB10

DB9

SW1

PD7

PD7

0

1

PA (Rx MODE)

PA OFF

PA ON

CR1

0

1

COUNTER RESET

NORMAL

RESET

DEMOD

RESET

CDR

RESET

SW1

0

1

Tx/Rx SWITCH

DEFAULT (ON)

OFF

PD6

0

1

DEMOD ENABLE

DEMOD OFF

DEMOD ON

PD5

0

1

ADC ENABLE

ADC OFF

ADC ON

LE1

0

1

LOG AMP ENABLE

LOG AMP OFF

LOG AMP ON

PD4

0

1

FILTER ENABLE

FILTER OFF

FILTER ON

PD3

0

1

LNA/MIXER ENABLE

LNA/MIXER OFF

LNA/MIXER ON

PD1

0

1

SYNTH STATUS

SYNTH OFF

SYNTH ON

Figure 40.

Register 8—Power Down Test Register Comments

•

It is not necessary to write to this register under normal operating conditions.

•

For a combined LNA/PA matching network, Bit R8_DB11 should always be set to 0, which enables the internal Tx_Rx switch. This is

the power-up default condition.