ADF7021 datasheet(20/44 Pages) AD

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ADF7021

Preliminary Technical Data

Rev. PrI | Page 20 of 44

IF – FDEV

IF + FDEV

LIMITERS

R4_DB(10:19)

R3_DB(10:17)

R4_DB(7)

R4_DB(9)

RxDATA

RxCLK

SLICER

FREQUENCY CORRELATOR

R4_DB(20:29)

Figure 21. FSK Correlator/Demodulator Block Diagram

Postdemodulator Filter

A second-order, digital low-pass filter removes excess noise

from the demodulated bit stream at the output of the

discriminator. The bandwidth of this postdemodulator filter is

programmable and must be optimized for the user’s data rate. If

the bandwidth is set too narrow, performance is degraded due

to intersymbol interference (ISI). If the bandwidth is set too

wide, excess noise degrades the receiver’s performance.

Typically, the 3 dB bandwidth of this filter is set at

approximately 0.75 times the user’s data rate, using Bits

R4_DB[20:29].

Bit Slicer

The received data is recovered by threshold detecting the output of

the postdemodulator low-pass filter. In the correlator/demodulator,

the binary output signal levels of the frequency discriminator are

always centered on 0. Therefore, the slicer threshold level can be

fixed at 0 and the demodulator performance is independent of

the run-length constraints of the transmit data bit stream. This

results in robust data recovery, which does not suffer from the

classic baseline wander problems that exist in the more traditional

FSK demodulators.

Frequency errors are removed by an internal AFC loop that

measures the average IF frequency at the limiter output and

applies a frequency correction value to the fractional-N

synthesizer. This loop should be activated when the frequency

errors are greater than approximately 40% of the transmit

frequency deviation.

Data Synchronizer

An oversampled digital PLL is used to resynchronize the

received bit stream to a local clock. The oversampled clock rate

of the PLL (CDR_CLK) must be set at 32 times the data rate.

See the Register 3—Transmit/Receive Clock Register section for

programming notes. The clock recovery PLL can accommodate

frequency errors of up to ±2%.

FSK Correlator Register Settings

To enable the FSK correlator/demodulator, Bits R4_DB[4:6]

should be set to 001. To achieve best performance, the

bandwidth of the 2FSK correlator must be optimized for the

specific deviation frequency that is used by the 2FSK

transmitter.

The discriminator BW is controlled in Register 4 by DB[10:19]

and is defined as

Discriminator_BW = DEMOD_CLK × K/(400 × 103)

where:

DEMOD_CLK is as defined in the Register 3—

Transmit/Receive Clock Register Comments section.

K = Round (100e3/Fdeviation) and Fdeviation is the 2FSK

frequency deviation in Hz.

To optimize the coefficients of the 2FSK correlator, Bits R4_DB7

and R4_DB[8:9] must be assigned. The value of these bits

depends on whether K is odd or even. These bits are assigned

according to Table 10 and Table 11.

Table 10. When K Is Even

K/2

R4_DB7

R4_DB[8:9]

Even

Odd

Table 11. When K Is Odd

(K + 1)/2

R4_DB7

R4_DB[8:9]

Odd

Even

Odd

Postdemodulator Bandwidth Register Settings

The 3 dB bandwidth of the postdemodulator filter is controlled

by Bits R4_DB[20:29] and is given by

CLK

DEMOD

Setting

Demod

Post

CUTOFF

where:

FCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator

filter. This should typically be set to 0.75 times the data rate (DR).

Some sample settings for the FSK correlator/demodulator are

DEMOD_CLK = 11.0592 MHz

DR = 9.6 kbps

FDEV = 4.8 kHz

therefore,

FCUTOFF = 0.75 × 9.6 × 103 Hz

Post_Demod_BW = 211 × π × 7.2 × 103 Hz/(11.0592 × 106)

Post_Demod_BW = Round(4.188) = 4

and

K = Round(100 kHz)/4.8 kHz) = 21

Discriminator_BW = (11.0592 × 106 × 21)/(400 × 103) =

580.6 = 581 (rounded to nearest integer)

Table 12. Example Register Settings

Setting Name

Value

Post_Demod_BW

R4_DB[20:29]

0x04

Discriminator BW

R4_DB[10:19]

0x245

Dot Product

R4_DB7

Rx Data Invert

R4_DB[8:9]

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