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Preliminary Technical Data

ADF7021

Rev. PrI | Page 15 of 44

TRANSMITTER

RF OUTPUT STAGE

The power amplifier (PA) of the ADF7021 is based on a single-

ended, controlled current, open-drain amplifier that has been

designed to deliver up to 13 dBm into a 50 Ω load at a

maximum frequency of 940 MHz.

The PA output current and, consequently, the output power are

programmable over a wide range. The PA configuration is shown

in Figure 14. The output power is set using Bits R2_DB[13:18].

IDAC

R2_DB(13:18)

R2_DB7

R2_DB(11:12)

RFGND

RFOUT

FROM VCO

R0_DB27

Figure 14. PA Configuration in FSK/GFSK Mode

The PA is equipped with overvoltage protection, which makes it

robust in severe mismatch conditions. Depending on the appli-

cation, users can design a matching network for the PA to

exhibit optimum efficiency at the desired radiated output power

level for a wide range of different antennas, such as loop or

mono-pole antennas. See the LNA/PA Matching section for

details.

PA Ramping

When the PA is switched on or off quickly, its changing input

impedance momentarily disturbs the VCO output frequency.

This process is called VCO pulling, and it manifests as spectral

splatter, or spurs in the output spectrum around the desired

carrier frequency. Some radio emissions regulations now place

limits on these PA transient-induced spurs (for example,

ETSI EN 300-220). By gradually ramping the PA on and off, PA

transient spurs can be minimized. The ADF7021 has built-in

PA ramping configurability. As Figure 15 illustrates, there are

eight ramp rate settings, defined as a certain number of PA

setting codes per one data-bit period. The PA steps through

each of its 64 code levels, but at different speeds for each setting.

The ramp rate is set by configuring Bits R2_DB[8:10].

If the PA is enabled/disabled by the PA_ENABLE bit in

turns hard off. If the PA is enabled/disabled by the TX_RX bit

in Register 0 (R0_DB27), it ramps up and down at the

programmed rate.

DATA BITS

PA RAMP 0

(NO RAMP)

PA RAMP 1

(256 CODES/BIT)

PA RAMP 2

(128 CODES/BIT)

PA RAMP 3

(64 CODES/BIT)

PA RAMP 4

(32 CODES/BIT)

PA RAMP 5

(16 CODES/BIT)

PA RAMP 6

(8 CODES/BIT)

PA RAMP 7

(4 CODES/BIT)

...

Figure 15. PA Ramping Settings

PA Bias Currents

Control Bits R2_DB[11:12] facilitate an adjustment of the PA

bias current to further extend the output power control range, if

necessary. If this feature is not required, the default value of

7 μA is recommended. If output power of greater than 10 dBm

is required, a PA bias setting of 11 μA is recommended. The

output stage is powered down by resetting Bit R2_DB7.

MODULATION SCHEMES

In all modulation schemes, an accurate clock is provided on the

DATA_CLK pin to latch the data from the microcontroller into

the transmit section at the exact required data rate. The exact

frequency of this clock is defined by:

DIVIDER

CDR

DIVIDER

DEMOD

XTAL

CLK

DATA

where:

XTAL is the crystal frequency.

DEMOD_DIVIDER is the divider that sets the demod-clock rate

(R3_DB[6:9]).

CDR_DIVIDER is the divider that sets the CDR clock rate

(R3_DB[10:17]).

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