ADF7021 datasheet(12/44 Pages) AD

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ADF7021

Preliminary Technical Data

Rev. PrI | Page 12 of 44

FREQUENCY SYNTHESIZER

REFERENCE INPUT

The on-board crystal oscillator circuitry (see Figure 7) can use

an inexpensive quartz crystal as the PLL reference. The oscil-

lator circuit is enabled by setting R1_DB12 high. It is enabled by

default on power-up and is disabled by bringing CE low. Errors

in the crystal can be corrected by using the automatic frequency

control feature or by adjusting the fractional-N value (see the N

Counter section). A single-ended reference (TCXO, CXO) can

also be used. The CMOS levels should be applied to OSC2 with

R1_DB12 set low.

OSC1

CP1

CP2

OSC2

Figure 7. Oscillator Circuit on the ADF7021

Two parallel resonant capacitors are required for oscillation at

the correct frequency. Their values are dependent upon the

crystal specification. They should be chosen to make sure that

the series value of capacitance added to the PCB track

capacitance adds up to the load capacitance of the crystal,

usually 18 pF to 20 pF. Track capacitance values vary from 2 pF

to 5 pF, depending on board layout. When possible, choose

capacitors that have a very low temperature coefficient to

ensure stable frequency operation over all conditions.

Programmable Crystal Bias Current

Bias current in the oscillator circuit can be configured between

20 μA and 35 μA by writing to Bits R1_DB[13:14].

CLKOUT Divider and Buffer

The CLKOUT circuit takes the reference clock signal from the

oscillator section, shown in Figure 7, and supplies a divided-

down 50:50 mark-space signal to the CLKOUT pin. An even

divide from 2 to 30 is available. This divide number is set in

R1_DB[7:10]. On power-up, the CLKOUT defaults to divide-by-8.

DVDD

CLKOUT

ENABLE BIT

CLKOUT

OSC1

DIVIDER

1TO 15

÷2

Figure 8. CLKOUT Stage

To disable CLKOUT, set the divide number to 0. The output

buffer can drive up to a 20 pF load with a 10% rise time at

4.8 MHz. Faster edges can result in some spurious feedthrough

to the output. A small series resistor (50 Ω) can be used to slow

the clock edges to reduce these spurs at FCLK.

R Counter

The 3-bit R counter divides the reference input frequency by an

integer from 1 to 7. The divided-down signal is presented as the

reference clock to the phase frequency detector (PFD). The

divide ratio is set in Register 1. Maximizing the PFD frequency

reduces the N value. This reduces the noise multiplied at a rate

of 20 log(N) to the output and reduces occurrences of spurious

components. Register 1 defaults to R = 1 on power-up:

PFD [Hz] = XTAL/R

Loop Filter

The loop filter integrates the current pulses from the charge

pump to form a voltage that tunes the output of the VCO to the

desired frequency. It also attenuates spurious levels generated by

the PLL. A typical loop filter design is shown in Figure 9.

CHARGE

PUMP OUT

VCO

Figure 9. Typical Loop Filter Configuration

The loop should be designed so that the loop bandwidth (LBW)

is approximately three times the data rate. Widening the LBW

excessively reduces the time spent jumping between

frequencies, but can cause insufficient spurious attenuation.

Narrow-loop bandwidths can result in the loop taking long

periods of time to attain lock. Careful design of the loop filter is

critical to obtain accurate modulation.

When using the Gaussian or raised cosine data filtering options,

it is recommended to use a LBW of 2.0 to 2.5 times the data rate

to ensure that sufficient samples of the input data are taken

while filtering system noise. The free design tool ADIsimPLL

can be used to design loop filters for the ADF7021.

N Counter

The feedback divider in the ADF7021 PLL consists of an 8-bit

integer counter and a 15-bit Σ-Δ fractional-N divider. The

integer counter is the standard pulse-swallow type common in

PLLs. This sets the minimum integer divide value to 23. The

fractional divide value gives very fine resolution at the output,

where the output frequency of the PLL is calculated as

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

−

Fractional

Integer

XTAL

OUT

When VCO divide-by-2 (see the Voltage Controlled Oscillator

(VCO) section) is selected, this formula becomes:

⎟

⎠

⎞

⎜

⎝

⎛

−

0.5

Fractional

Integer_N

XTAL

OUT

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