MPC505

MOTOROLA

MPC505ADI/D

5

INSTRUCTION CACHE

The MPC505 instruction cache (I-cache) is a 4-Kbyte, 2-way set associative cache. The cache is

organized into 128 sets, with two lines per set and four words per line. Cache lines are aligned on

four-word boundaries in memory.

A cache access cycle begins with an instruction request from the CPU instruction unit. In case of a

cache hit, the instruction is delivered to the instruction unit. In case of a cache miss, the cache ini-

tiates a burst read cycle (four beats per burst, one word per beat) on the instruction bus (I-bus) with

the address of the requested instruction. The first word received from the bus is the requested in-

struction. The cache forwards this instruction to the instruction unit as soon as it is received from

the I-bus. A cache line is then selected to receive the data which will be coming from the bus. An

LRU (least recently used) replacement algorithm is used to select a line when no empty lines are

available.

Each cache line can be used as an SRAM, allowing the application to lock critical code segments

that need fast and deterministic execution time.

Major features of the I-cache include the following:

• 4 Kbytes, 2-way set associative, 4 words in a line

• LRU replacement policy

• Lockable SRAM (cache line granularity)

• Critical word first burst access

• Stream hit (allows fetch from the burst buffer and of the word currently on the I-bus)

• Efficiently utilizes the pipeline of the I-bus by initiating a new burst cycle (if miss is detected)

while bringing the tail of the previous missed line

• Cache control:

— Supports PowerPC invalidate instruction

— Supports load & lock (cache line granularity)

• Supports cache inhibit:

— as a cache mode of operation (cache disable)

— on memory regions (supported by the chip select logic)

• Miss latency is reduced by

— sending address to the cache and to the I-bus simultaneously; and

— aborting on cache hit before cycle goes external

• Minimum operational power consumption

• Read capability of tags (including all attributes) and data arrays for debugging purposes

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com