MOTOROLA

MPC505

6

MPC505ADI/D

SYSTEM INTERFACE UNIT

The system interface unit (SIU) consists of several blocks. These blocks control the buses of the

chip, provide the clocks, and provide miscellaneous functions for the system, such as chip selects,

test control, reset control, and I/O ports.

The MPC505 has an internal Harvard architecture and a single external bus. The internal buses are

the instruction bus (I-bus) and the load/store bus (L-bus). The external bus interface (EBI) connects

each of these internal buses with the external bus (E-bus). The chip select block provides user-pro-

grammable chip selects to select external memory or peripherals. The clock block controls the gen-

eration of the system clocks and such features as programmability of the clocks and low-power

modes. The reset control function interfaces to the reset pins and provides a reset status register.

The I/O ports provide untimed I/O functions on pins that are not used for their primary function.

External Bus Interface

The external bus interface (EBI) interfaces the external bus (E-bus) with the two internal buses

(I-bus and L-bus). The E-bus can perform synchronous, pipeline, or burst transfers. Signals driven

onto the E-bus are required to meet the set-up and hold times relative to the bus clock’s rising edge.

The bus has the ability to support multiple masters, but its protocol is optimized for a single-proces-

sor environment.

Major features of the EBI include the following:

• No external glue logic required for a simple system.

• Supports a variety of memory devices (SRAM, EEPROM).

• Fast (one-clock) arbitration possible.

• Bus is synchronous — all signals are referenced to the rising edge of the bus clock.

• 32-bit data bus, 32-bit address bus with byte enables.

• Protocol allows wait states to be inserted before handshaking signals are asserted.

• Supports 16- and 32-bit devices.

• Bus electrical specification minimizes system power consumption.

Chip Selects

Typical microcontrollers require additional hardware to provide external chip-select signals. On the

MPC505, the chip-select logic controls the peripheral devices of typical uniprocessor systems. This

allows users to implement simple systems without the need to design any external glue logic.

Major features of the chip-select module include the following:

• No external glue logic required for typical systems if the chip-select module is used.

• Modular architecture for ease of expansion.

• Pins are programmable as chip enables, output enables, or write enables.

• Supports multiple regions, with each region having programmable attributes.

• Up to seven programmable wait states for slave devices.

• Programmable address range, block size.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com