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MPC505ADI/D

MPC505

Advance Information

PowerPC™ MPC505 RISC Microcontroller

The MPC505 is the first implementation of a family of reduced instruction set computer (RISC) mi-

crocontrollers based on the PowerPC ArchitectureTM. The MPC505 implements the 32-bit portion

of the PowerPC Architecture, which provides 32-bit effective addresses, integer data types of 8, 16,

and 32 bits, and floating-point data types of 32 and 64 bits.

The RISC MCU processor (RCPU) integrates four execution units: an integer unit (IU), a load/store

unit (LSU), a branch processing unit (BPU), and a floating-point unit (FPU). The RCPU is capable

of issuing one instruction per clock. Instructions can complete out of order for increased perfor-

mance; however, the MPC505 makes them appear sequential.

The MPC505 includes an on-chip, 4-Kbyte, two-way set associative, physically addressed instruc-

tion cache; chip-select logic to reduce or eliminate external decoding logic; 4 Kbytes of static RAM;

and extensive processor debugging functionality.

The MPC505 has a high-bandwidth, 32-bit data bus and a 32-bit address bus. The MCU supports

16- and 32-bit memories. Single-beat and burst data memory accesses are supported.

The MPC505 uses an advanced, 3.3-V CMOS process technology.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com