MOTOROLA

MPC505

8

MPC505ADI/D

PERIPHERAL CONTROL UNIT

The peripheral control unit (PCU) consists of the following submodules:

• Software watchdog — provides system protection.

• Interrupt controller — controls the interrupts that external peripherals and internal modules

send to the CPU.

• Port Q — provides for digital I/O on pins that are not being used as interrupt inputs.

• L-bus/IMB2 interface (LIMB) — provides an interface between the load/store bus and the sec-

ond generation intermodule bus (IMB2). The IMB2, which is comparable to the IMB in the

modular 68300 and M68HC16 families, connects on-chip peripherals to the processor via the

LIMB.

Interrupt Controller

The interrupt controller consolidates all the interrupt sources into a single interrupt signal to the pro-

cessor. The interrupt controller supports up to 32 maskable interrupt levels. Each external interrupt

request (IRQ) input can be made edge-sensitive or level-sensitive. The interrupt controller uses the

following registers:

• IRQPEND — Contains a status bit for each of the 32 interrupt levels. Each bit of IRQPEND is

a read-only status bit that reflects the current state of the corresponding interrupt signal.

• IRQENABLE — Contains an enable bit for each of the 32 interrupt levels.

• IRQAND — Logical AND of the IRQPEND and IRQENABLE registers. This register reflects

which levels are actually causing the IRQ input to the processor to be asserted.

• IRQLEVELS — Contains three 5-bit fields that determine the interrupt request levels of the

PIT and the external interrupt request signals.

The interrupt controller does not enforce a priority scheme. All interrupt priority is determined by the

software. In this way, the system is not limited to a particular interrupt priority scheme.

Software Watchdog

The software watchdog monitors the system software interface and requires the software to take

periodic action in order to communicate that it is executing properly. To protect against software

error, the following service sequence must be executed on a regular basis:

1.

Write 0x556C to the SWSR

2.

Write 0xAA39 to the SWSR

This sequence clears the watchdog timer, and the timing process begins again. If this periodic ser-

vicing does not occur, the software watchdog issues a reset. If any value other than 0x556C or

0xAA39 is written to the SWSR, the service sequence must start over.

Port Q

When not used as interrupt inputs, interrupt request (IRQ) pins can be used for digital I/O. The fol-

lowing registers control port Q operation:

• Port Q Pin Assignment Register (PQPAR) — Allows the user to configure each pin as a digital

input, digital output, edge- or level-sensitive interrupt request to the CPU, or edge- or level-

sensitive interrupt request to the interrupt controller.

• Port Q Data Register (PORTQ) — Monitors or controls the state of its pins, depending on the

encoding for each pin in the PQPAR. PORTQ and PORTQE make up the PQEDGDAT reg-

ister.

• Port Q Edge-Detect Status Register (PORTQE) — Monitors when the proper transition occurs

on a port Q or interrupt request pin. PORTQ and PORTQE make up the PQEDGDAT register.

Freescale Semiconductor, Inc.

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