NXP Semiconductors

NVT2001; NVT2002

Bidirectional voltage level translator for open-drain and push-pull applications

7.4 How to design for maximum frequency operation

The maximum frequency is limited by the minimum pulse width LOW and HIGH as well as rise time and fall

time. See Equation 1 as an example of the maximum frequency. The rise and fall times are shown in Figure 9.

(1)

002aag912

tr(actual)

tf(actual)

GND

VOL

VIL

VIH

VCC

tHIGH(min)

tLOW(min)

1 / fmax

0.9 × VCC

0.1 × VCC

Figure 9. An example waveform for maximum frequency

The rise and fall times are dependent upon translation voltages, the drive strength, the total node capacitance

(CL(tot)) and the pull-up resistors (RPU) that are present on the bus. The node capacitance is the addition of the

PCB trace capacitance and the device capacitance that exists on the bus. Because of the dependency of the

external components, PCB layout and the different device operating states the calculation of rise and fall times

is complex and has several inflection points along the curve.

The main component of the rise and fall times is the RC time constant of the bus line when the device is in its

two primary operating states: when device is in the ON state and it is low-impedance, the other is when the

device is OFF isolating the A-side from the B-side.

A description of the fall time applied to either An or Bn output going from HIGH to LOW is as follows. Whichever

side is asserted first, the B-side down must discharge to the VCC(A) voltage. The time is determined by the pull-

up resistor, pull-down driver strength and the capacitance. As the level moves below the VCC(A) voltage, the

channel resistance drops so that both A and B sides equal. The capacitance on both sides is connected to

form the total capacitance and the pull-up resistors on both sides combine to the parallel equivalent resistance.

The Ron of the device is small compared to the pull-up resistor values, so its effect on the pull-up resistance

can be neglected and the fall is determined by the driver pulling the combined capacitance and pull-up resistor

currents. An estimation of the actual fall time seen by the device is equal to the time it takes for the B-side to fall

to the VCC(A) voltage and the time it takes for both sides to fall from the VCC(A) voltage to the VIL level.

A description of the rise time applied to either An or Bn output going from LOW to HIGH is as follows. When

the signal level is LOW, the Ron is at its minimum, so the A and B sides are essentially one node. They will rise

together with an RC time constant that is the sum of all the capacitance from both sides and the parallel of the

resistance from both sides. As the signal approaches the VCC(A) voltage, the channel resistance goes up and

the waveforms separate, with the B side finishing its rise with the RC time constant of the B side. The rise to

VCC(A) is essentially the same for both sides.

There are some basic guidelines to follow that will help maximize the performance of the device:

• Keep trace length to a minimum by placing the NVT device close to the processor.

• The signal round trip time on trace should be shorter than the rise or fall time of signal to reduce reflections.

• The faster the edge of the signal, the higher the chance for ringing.

• The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher the frequency the device

can use.

The system designer must design the pull-up resistor value based on external current drive strength and

limit the node capacitance (minimize the wire, stub, connector and trace length) to get the desired operation

frequency result.

NVT2001_NVT2002

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Product data sheet

Rev. 4.4 — 22 May 2023

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