ADV7393 datasheet(41/96 Pages) AD

41 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 41 of 96

ADV7390/ADV7391 INPUT CONFIGURATION

The ADV7390/ADV7391 supports a number of different input

modes. The desired input mode is selected using Subaddress 0x01,

Bits[6:4]. The ADV7390/ADV7391 defaults to standard

definition (SD) mode upon power-up. Table 30 provides an

overview of all possible input configurations. Each input mode

is described in detail in this section.

Table 30. ADV7390/ADV7391 Input Configuration

Input Mode

000

YCrCb

010

ED/HD-DDR

YCrCb

111

ED (at 54 MHz)

YCrCb

STANDARD DEFINITION

Subaddress 0x01, Bits[6:4] = 000

SD YCrCb data can be input in an interleaved 4:2:2 format over

an 8-bit bus rate of 27 MHz.

A 27 MHz clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

the HSYNC and VSYNC pins. Embedded EAV/SAV timing

codes are also supported. The ITU-R BT.601/656 input standard

is supported.

The interleaved pixel data is input on Pin P7 to Pin P0, with P0

being the LSB.

MPEG2

DECODER

CLKIN

P[7:0]

27MHz

YCrCb

ADV7390/

ADV7391

VSYNC,

HSYNC

Figure 49. SD Example Application

ENHANCED DEFINITION/HIGH DEFINITION

Subaddress 0x01, Bits[6:4] = 010

ED or HD YCrCb data can be input in an interleaved 4:2:2

format over an 8-bit DDR bus.

The clock signal must be provided on the CLKIN pin. If

required, external synchronization signals can be provided on

the HSYNC and VSYNC pins. Embedded EAV/SAV timing

codes are also supported.

8-Bit 4:2:2 ED/HD YCrCb Mode (DDR)

In 8-bit DDR 4:2:2 YCrCb input mode, the Y pixel data is input

on Pin P7 to Pin P0 upon either the rising or falling edge of

CLKIN. P0 is the LSB.

The CrCb pixel data is also input on Pin P7 to Pin P0

upon the opposite edge of CLKIN. P0 is the LSB.

Whether the Y data is clocked in upon the rising or falling edge

of CLKIN is determined by Subaddress 0x01, Bits[2:1] (see

Figure 50 and Figure 51).

3FF

Cr0

CLKIN

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 00 IN THIS CASE.

P[7:0]

Cb0

Figure 50. ED/HD-DDR Input Sequence (EAV/SAV)—Option A

3FF

Cb0

Cr0

CLKIN

P[7:0]

NOTES

1. SUBADDRESS 0x01 [2:1] SHOULD BE SET TO 11 IN THIS CASE.

Figure 51. ED/HD-DDR Input Sequence (EAV/SAV)—Option B

MPEG2

DECODER

CLKIN

P[7:0]

INTERLACED TO

PROGRESSIVE

YCrCb

ADV7390/

ADV7391

VSYNC,

HSYNC

YCrCb

Figure 52. ED/HD-DDR Example Application

ENHANCED DEFINITION (AT 54 MHz)

Subaddress 0x01, Bits[6:4] = 111

ED YCrCb data can be input in an interleaved 4:2:2 format over

an 8-bit bus rate of 54 MHz.

A 54 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes are supported. External

synchronization signals are not supported in this mode.

The interleaved pixel data is input on Pin P7 to Pin P0, with P0

being the LSB.

3FF

Cb0

Cr0

CLKIN

P[7:0]

Figure 53. ED (At 54 MHz) Input Sequence (EAV/SAV)

ADV7393 Datasheet(PDF) 41 Page - Analog Devices

ADV7393 Datasheet(HTML) 41 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL