ADV7393 datasheet(48/96 Pages) AD

48 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 48 of 96

Programming the FSC

The subcarrier frequency register value is divided into four FSC

registers as shown in the previous example. The four subcarrier

frequency registers must be updated sequentially, starting with

Subcarrier Frequency Register 0 and ending with Subcarrier

Frequency Register 3. The subcarrier frequency updates only

after the last subcarrier frequency register byte has been

received by the ADV739x.

Typical FSC Values

Table 37 outlines the values that should be written to the

subcarrier frequency registers for NTSC and PAL B/D/G/H/I.

Table 37. Typical FSC Values

Subaddress

Description

NTSC

PAL B/D/G/H/I

0x8C

FSC0

0x1F

0xCB

0x8D

FSC1

0x7C

0x8A

0x8E

FSC2

0xF0

0x09

0x8F

FSC3

0x21

0x2A

SD NONINTERLACED MODE

Subaddress 0x88, Bit 1

The ADV739x supports a SD noninterlaced mode. Using this

mode, progressive inputs at twice the frame rate of NTSC and

PAL (240p/59.94 Hz and 288p/50 Hz, respectively) can be input

into the ADV739x. The SD noninterlaced mode can be enabled

using Subaddress 0x88, Bit 1.

A 27 MHz clock signal must be provided on the CLKIN pin.

Embedded EAV/SAV timing codes or external horizontal and

vertical synchronization signals provided on the HSYNC and

VSYNC pins can be used to synchronize the input pixel data.

All input configurations, output configurations, and features

available in NTSC and PAL modes are available in SD noninter-

laced mode.

For 240p/59.94 Hz input, the ADV739x should be configured for

NTSC operation and Subaddress 0x88, Bit 1 should be set to 1.

For 288p/50 Hz input, the ADV739x should be configured for

PAL operation and Subaddress 0x88, Bit 1 should be set to 1.

SD SQUARE PIXEL MODE

Subaddress 0x82, Bit 4

The ADV739x can be used to operate in square pixel mode

(Subaddress 0x82, Bit 4). For NTSC operation, an input clock of

24.5454 MHz is required. Alternatively, for PAL operation, an

input clock of 29.5 MHz is required. The internal timing logic

adjusts accordingly for square pixel mode operation.

In square pixel mode, the timing diagrams shown in Figure 65

and Figure 66 apply.

Y Cr Y

Y C

EAV CODE

SAV CODE

ANCILLARY DATA

(HANC)

4 CLOCK

272 CLOCK

1280 CLOCK

4 CLOCK

344 CLOCK

1536 CLOCK

END OF ACTIVE

VIDEO LINE

START OF ACTIVE

VIDEO LINE

ANALOG

VIDEO

INPUT PIXELS

NTSC/PAL M SYSTEM

(525 LINES/60Hz)

PAL SYSTEM

(625 LINES/50Hz)

Figure 65. Square Pixel Mode EAV/SAV Embedded Timing

FIELD

PIXEL

DATA

PAL = 308 CLOCK CYCLES

NTSC = 236 CLOCK CYCLES

HSYNC

Figure 66. Square Pixel Mode Active Pixel Timing

ADV7393 Datasheet(PDF) 48 Page - Analog Devices

ADV7393 Datasheet(HTML) 48 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL