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ADV7393 Datasheet(PDF) 94 Page - Analog Devices |
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ADV7393 Datasheet(HTML) 94 Page - Analog Devices |
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94 / 96 page  ADV7390/ADV7391/ADV7392/ADV7393 Rev. 0 | Page 94 of 96 Table 117. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x2C 720p @ 60 Hz/59.94 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. Table 118. 10-Bit 720p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x2C 720p @ 60 Hz/59.94 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. 0x33 0x6C 10-bit input enabled. Table 119. 8-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x6C 1080i @ 30 Hz/29.97 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. Table 120. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x6C 1080i @ 30 Hz/29.97 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. 0x33 0x6C 10-bit input enabled. Table 121. 8-Bit 1080i YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x6C 1080i @ 30 Hz/29.97 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. Table 122. 10-Bit 1080i YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x6C 1080i @ 30 Hz/29.97 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. 0x33 0x6C 10-bit input enabled. |
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