ADV7393 datasheet(76/96 Pages) AD

76 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 76 of 96

PIXEL

DATA

HSYNC

VSYNC

PAL = 132 × CLOCK/2

NTSC = 122 × CLOCK/2

PAL = 864 × CLOCK/2

NTSC = 858 × CLOCK/2

Figure 112. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave)

Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1)

In this mode, the ADV739x accepts or generates horizontal synchronization and odd/even field signals. When HSYNC is high, a

transition of the field input indicates a new frame, that is, vertical retrace. The ADV739x automatically blanks all normally blank lines as

per CCIR-624. HSYNC and VSYNC are output in master mode and input in slave mode on the HSYNC and VSYNC pins, respectively.

260

261

262

263

264

265

266

267

268

269

270

271

272

273

274

283

284

285

ODD FIELD EVEN FIELD

DISPLAY

VERTICAL BLANK

522

523

524

525

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

HSYNC

FIELD

HSYNC

FIELD

Figure 113. SD Timing Mode 3, NTSC

622

623

624

625

621

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

309

310

311

312

313

314

315

316

317

318

319

334

335

336

DISPLAY

VERTICAL BLANK

ODD FIELD

EVEN FIELD

FIELD

DISPLAY

320

HSYNC

Figure 114. SD Timing Mode 3, PAL

ADV7393 Datasheet(PDF) 76 Page - Analog Devices

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