ADV7393 datasheet(60/96 Pages) AD

60 / 96 page

ADV7390/ADV7391/ADV7392/ADV7393

Rev. 0 | Page 61 of 96

EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL

For timing synchronization purposes, the ADV739x is able to accept either EAV/SAV time codes embedded in the input pixel data or

external synchronization signals provided on the HSYNC and VSYNC pins (see Table 48). It is also possible to output synchronization

signals on the HSYNC and VSYNC pins (see Table 49 to Table 51).

Table 48. Timing Synchronization Signal Input Options

Signal

Condition

SD HSYNC In

HSYNC

SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).1

SD VSYNC/FIELD In

VSYNC

SD Slave Timing Mode 1, Mode 2, or Mode 3 Selected (Subaddress 0x8A[2:0]).1

ED/HD HSYNC In

HSYNC

ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).

ED/HD VSYNC/FIELD In

VSYNC

ED/HD Timing Synchronization Inputs Enabled (Subaddress 0x30, Bit 2 = 0).

1 SD and ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02[7:6] = 00).

Table 49. Timing Synchronization Signal Output Options

Signal

Condition

SD HSYNC Out

HSYNC

SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).1

SD VSYNC/FIELD Out

VSYNC

SD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 6 = 1).1

ED/HD HSYNC Out

HSYNC

ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).2

ED/HD VSYNC/FIELD Out

VSYNC

ED/HD Timing Synchronization Outputs enabled (Subaddress 0x02, Bit 7 = 1).2

1 ED/HD timing synchronization outputs must also be disabled (Subaddress 0x02, Bit 7 = 0).

2 ED/HD timing synchronization inputs must also be disabled, that is, embedded EAV/SAV timing codes must be enabled (Subaddress 0x30, Bit 2 = 1).

Table 50. HSYNC Output Control1

ED/HD Input Sync

Format (0x30, Bit 2)

ED/HD HSYNC

Control

(0x34, Bit 1)

ED/HD Sync

Output Enable

(0x02, Bit 7)

SD Sync

Output Enable

(0x02, Bit 6)

Signal on HSYNC Pin

Duration

Tristate.

–

Pipelined SD HSYNC.

See Error! Reference

source not found..

Pipelined ED/HD HSYNC.

As per HSYNC timing.

Pipelined ED/HD HSYNC based on

AV Code H bit.

Same as line blanking

interval.

Pipelined ED/HD HSYNC based on

horizontal counter.

Same as embedded

HSYNC.

1 In all ED/HD standards where there is a HSYNC output, the start of the HSYNC pulse is aligned with the falling edge of the embedded HSYNC in the output video.

Table 51. VSYNC Output Control1

ED/HD Input

Sync Format

(0x30, Bit 2)

ED/HD VSYNC

Control

(0x34, Bit 2)

ED/HD Sync

Output Enable

(0x02, Bit 7)

SD Sync

Output Enable

(0x02, Bit 6)

Video Standard

Signal on VSYNC Pin

Duration

Tristate.

–

Interlaced

Pipelined SD VSYNC/Field.

See Error!

Reference source

not found..

Pipelined ED/HD VSYNC

or field signal.

As per VSYNC or

Field signal timing.

All HD interlaced

standards

Pipelined Field signal

based on AV Code F bit.

Field.

All ED/HD progressive

standards

Pipelined VSYNC based on

AV Code V bit.

Vertical blanking

interval.

All ED/HD standards

except 525p

Pipelined ED/HD VSYNC

based on vertical counter.

Aligned with

serration lines.

525p

Pipelined ED/HD VSYNC

based on vertical counter.

Vertical blanking

interval.

1 In all ED/HD standards where there is a VSYNC output, the start of the VSYNC pulse is aligned with the falling edge of the embedded VSYNC in the output video.

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