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ST7789V2 Datasheet(PDF) 272 Page - Sitronix Technology Co., Ltd. |
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ST7789V2 Datasheet(HTML) 272 Page - Sitronix Technology Co., Ltd. |
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272 / 319 page  ST7789V2 Version 1.0 Page 272 of 319 2016/11 Sitronix Confidential The information contained herein is the exclusive property of Sitronix and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of Sitronix. In rgb interface, if the setting of gate off timing is more than the number of dotclk in one line, the gate off timing is determined by hsync. GOF[3:0]: Gate off timing adjustment Gate off timing=-GOF[3:0]*400ns Register Availability Status Availability Normal Mode On, Idle Mode Off, Sleep Out Yes Normal Mode On, Idle Mode On, Sleep Out Yes Partial Mode On, Idle Mode Off, Sleep Out Yes Partial Mode On, Idle Mode On, Sleep Out Yes Sleep In Yes Default Status Default Value Power On Sequence 2Ah/2Bh/22h/75h S/W Reset 2Ah/2Bh/22h/75h H/W Reset 2Ah/2Bh/22h/75h |
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