DP83849IF datasheet(44/108 Pages) NSC

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5.5 Power Feedback Circuit

To ensure correct operation for the DP83849IF, parallel

caps with values of 10

µF and 0.1 µF should be placed

close to pin 31 (PFBOUT) of the device. Pin 7 (PFBIN1),

pin 28 (PFBIN2), pin 34 (PFBIN3) and pin 54 (PFBIN4)

must be connected to pin 31 (PFBOUT), each pin requires

a small capacitor (.1

µF). See Figure 15 below for proper

connections.

5.6 Power Down/Interrupt

The Power Down and Interrupt functions are multiplexed

on pin 18 and pin 44 of the device. By default, this pin func-

tions as a power down input and the interrupt function is

disabled. Setting bit 0 (INT_OE) of MICR (11h) will config-

ure the pin as an active low interrupt output. Ports A and B

can be powered down individually, using the separate

PWRDOWN_INT_A and PWRDOWN_INT_B pins.

5.6.1 Power Down Control Mode

The PWRDOWN_INT pins can be asserted low to put the

device in a Power Down mode. This is equivalent to setting

bit 11 (Power Down) in the Basic Mode Control Register,

BMCR (00h). An external control signal can be used to

drive the pin low, overcoming the weak internal pull-up

resistor. Alternatively, the device can be configured to ini-

tialize into a Power Down state by use of an external pull-

down resistor on the PWRDOWN_INT pin. Since the

device will still respond to management register accesses,

setting the INT_OE bit in the MICR register will disable the

PWRDOWN_INT input, allowing the device to exit the

Power Down state.

Table 16. 25 MHz Crystal Specification

Parameter

Min

Typ

Max

Units

Condition

Frequency

MHz

Frequency

Tolerance

+50

ppm

Operational Temperature

Frequency

Stability

+50

ppm

1 year aging

Load Capacitance

µF

Pin 31 (PFBOUT)

µF

Pin 7 (PFBIN1)

Pin 28 (PFBIN2)

µF

Pin 34 (PFBIN3)

Pin 54 (PFBIN4)

Figure 15. Power Feeback Connection

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