DP83849IF datasheet(70/108 Pages) NSC

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7.2.4 RMII and Bypass Register (RBR)

This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single

Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath selection for

Transmit and Receive in multiport applications.

Table 36. RMII and Bypass Register (RBR), addresses 17h

Bit

Bit Name

Default

Description

SIM_WRITE

0, RW

Simultaneous Write:

Setting this bit in port A register space enables simultaneous write to Phy

registers in both ports. Subsequent writes to port A registers will write to

registers in both ports A and B.

1 = Simultaneous writes to both ports

0 = Per-port write

RESERVED

0, RO

RESERVED: Writes ignored, Read as 0

DIS_TX_OPT

0, RW

Disable RMII TX Latency Optimization:

Normally the RMII Transmitter will minimize the transmit latency by

realigning the transmit clock with the Reference clock phase at the

start of a packet transmission. Setting this bit will disable Phase re-

alignment and ensure that IDLE bits will always be sent in multiples

of the symbol size. This will result in a larger uncertainty in RMII

transmit latency.

12:11

RX_PORT

00, RW

Receive Port:

See Section 3.5 for more information on Flexible Port Switching.

10:9

TX_SOURCE

Strap, RW

Transmit Source:

See Section 3.5 for more information on Flexible Port Switching.

00 = Not strapped for Extender Mode

10 = Strapped for Extender Mode

PMD_LOOP

0, RW

PMD Loopback:

0= Normal Operation

1= Remote (PMD) Loopback

Setting this bit will cause the device to Loopback data received

from the Physical Layer. The loopback is done prior to the MII or

RMII interface. Data received at the internal MII or RMII interface

will be applied to the transmitter. This mode should only be used if

RMII mode or Single Clock MII mode is enabled.

SCMII_RX

Strap, RW

Single Clock RX MII Mode:

0= Standard MII mode

1= Single Clock RX MII Mode

Setting this bit will cause the device to generate receive data

(RX_DV, RX_ER, RXD[3:0]) synchronous to the X1 Reference

clock. RX_CLK is not used in this mode. This mode uses the RMII

elasticity buffer to tolerate variations in clock frequencies. This bit

cannot be set if RMII_MODE is set to a 1. This bit is strapped to 1

if EXTENDER_EN is 1 and RMII Mode is not strapped at hard re-

set.

SCMII_TX

Strap, RW

Single Clock TX MII Mode:

0= Standard MII mode

1= Single Clock TX MII Mode

Setting this bit will cause the device to sample transmit data

(TX_EN, TXD[3:0]) synchronous to the X1 Reference clock.

TX_CLK is not used in this mode. This bit cannot be set if

RMII_MODE is set to a 1. This bit is strapped to 1 if

EXTENDER_EN is 1 and RMII Mode is not strapped at hard reset.

DP83849IF Datasheet(PDF) 70 Page - National Semiconductor (TI)

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