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CDB5378 Datasheet(PDF) 22 Page - Cirrus Logic |
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CDB5378 Datasheet(HTML) 22 Page - Cirrus Logic |
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22 / 72 page ![]() CDB5378 22 DS639DB3 2.3.1.2 Configuration - SPI Port On CDB5378, configuration of the digital filter is through the SPI port by the on-board 8051 microcontrol- ler, which receives commands from the PC evaluation software via the USB interface. Evaluation software commands can write/read digital filter registers, specify digital filter coefficients and start/stop digital filter operation. Alternately, the digital filter can automatically load configuration information from an on-board serial EEPROM. The configuration method for the digital filter is selected by the BOOT signal from a dip switch (S1, #4). By default the BOOT signal is set low (S1, #4 - LO) to indicate configuration information is written by the microcontroller. If BOOT is instead set high (S1, #4 - HI), the digital filter attempts to automatically read configuration information from the serial EEPROM after reset. Configuration information is initially written into the serial EEPROM by jumpering its chip select input (EECS) to the microcontroller chip select output (SS) and sending EEPROM programming commands and data from the PC evaluation software. 2.3.1.3 Phase Locked Loop To make synchronous analog measurements throughout a distributed system, a synchronous system clock is required to be provided to each measurement node. For evaluation testing purposes, a BNC clock input on CDB5378 can receive an external system clock and create a synchronous local clock using the CS5378 PLL. The system clock into the BNC clock input is applied to the CS5378 CLK input by selecting CLK_EXT on the DIGITAL FILTER CLOCK jumper (J16). The CS5378 PLL input frequency is specified at reset by the state of the GPIO[4..6]:PLL[0..2] pins, as detailed in the CS5378 data sheet. Specification Value Input Clock Frequency 1.024, 2.048, 4.096 MHz Distributed Clock Synchronization ± 240 ns Maximum Input Clock Jitter, RMS 1 ns Specification Value PLL Internal Clock Frequency 32.768 MHz Maximum Jitter, RMS 300 ps Loop Filter Architecture Internal |
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