Frame 1 Two-Wire Target Address Byte

Frame 2 Register Pointer Byte

1

Start By

Controller

ACK By

Target

ACK By

Target

1

9

1

9

SDA

SCL

0

0

A3

A2

A1

A0

R/W

P7

P6

P5

P4

P3

P2

P1

P0

Stop

A.

The value of the target address byte is determined by the settings of the A0 and A1 pins. Refer to Table 7-2.

Figure 7-11. Typical Register Pointer Set

7.5.1.2 High-Speed I2C Mode

When the bus is idle, both the SDA and SCL lines are pulled high by the pullup resistors. The controller

generates a start condition followed by a valid serial byte containing high-speed (HS) controller code 00001XXX.

This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The

INA741 does not acknowledge the HS controller code, but the INA741 does recognize the code and switches the

internal filters to support 2.94-MHz operation.

The controller then generates a repeated start condition (a repeated start condition has the same timing as

the start condition). After this repeated start condition, the protocol is the same as F/S mode, except that

transmission speeds up to 2.94 MHz are allowed. Instead of using a stop condition, use repeated start conditions

to maintain the bus in HS-mode. A stop condition ends the HS-mode and switches all the internal filters of the

device to support the F/S mode.

7.5.1.3 SMBus Alert Response

The INA741 is designed to respond to the SMBus Alert Response address. The SMBus Alert Response provides

a quick fault identification for simple targets. When an Alert occurs, the controller can broadcast the Alert

Response target address (0001 100) with the Read/Write bit set high. Following this Alert Response, any target

that generates an alert identifies itself by acknowledging the Alert Response and sending its address on the bus.

The Alert Response can activate several different targets simultaneously, similar to the I2C General Call. If

more than one target attempts to respond, bus arbitration rules apply. The losing device does not generate an

Acknowledge and continues to hold the Alert line low until that device wins arbitration.

7.6 Register Maps

7.6.1 INA741 Registers

Table 7-3 lists the INA741 registers. All register locations not listed in Table 7-3 should be considered as

reserved locations and the register contents should not be modified.

Table 7-3. INA741 Registers

Address Acronym

Register Name

Register Size (bits)

Section

0h

CONFIG

Configuration

16

Go

1h

ADC_CONFIG

ADC Configuration

16

Go

5h

VBUS

Bus Voltage Measurement

24

Go

6h

DIETEMP

Temperature Measurement

16

Go

7h

CURRENT

Current Result

24 (4 reserved)

Go

8h

POWER

Power Result

24

Go

9h

ENERGY

Energy Result

40

Go

Ah

CHARGE

Charge Result

40

Go

Bh

DIAG_ALRT

Diagnostic Flags and Alert

16

Go

Ch

COL

Current Over-Limit Threshold

16

Go

Dh

CUL

Current Under-Limit Threshold

16

Go

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INA741

SBOSAC2 – JULY 2023

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