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UPB1007K Datasheet(PDF) 6 Page - Renesas Technology Corp |
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UPB1007K Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 27 page ![]() PIN EXPLANATION Pin No. Pin Name Function and Application Internal Equivalent Circuit 1 GND LNA Ground pin of LNA. 2 LNAin Input pin of low noise amplifier. It is a single-ended open collector design. Capacitive coupling is required; external matching will improve gain or NF. 36 2 1 3 Regulator VCC 6.5 k Ω 3 VCCrf Supply voltage pin of LNA, RF mixer and VCO voltage regulator. 4 GNDLO Ground pin of 1stLO oscillator circuit and RF Mixer. 5 1stLO-OSC1 6 1stLO-OSC2 Pin 5 & 6 are base pins of the differential amplifier for 1stLO oscillator. These pins requre an LC (varacator) tank circuit to oscilate at around 1 400 MHz. 7 VCCLO Supply voltage pin of oscillator circuit for 1stLO oscillator and RF mixer. 7 6 4 3 Regulator VCC 4.4 k Ω 1.8 pF 1.8 pF 4.4 k Ω 400 Ω 400 Ω 410 Ω 5 idc = 941 µ 8 PDout This is a cirrent mode charge pump output. For connection to a passive RC loop filter for driving external varactor diode of 1stLO oscillator. 9 VCCdig Supply voltage pin of digital portion of the chip. 8 Source Control Sink Control ESD ESD 9 11 Data Sheet PU10282EJ01V0DS 4 µPB1008K |
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