UPB1007K datasheet(9/27 Pages) RENESAS

9 / 27 page

No.

Pin Name

Function and Application

Internal Equivalent Circuit

DCoffsetlb

DC offset compensation pin for

l-bar arm. A low pass capacitor

shunt to pin 25 is required.

DCoffsetl

DC offset compensation pin for

I-bar arm. A low pass capacitor

shunt to pin 24 is required.

See pin 16 & 17 schematic

2ndIFout-Ib

2ndIFout-I

Differential output pins of

quadrature demodulator I

output. Adding a lowpass shunt

capacitor between these pins

will define the IF bandwidth.

See pin 14 & 15 schematic

VCCanalog

Supply voltage pin of analog

portion of the chip.

VAGC

Gain control voltage pin of IF

amplifier. This voltage performs

reverse control, (i.e., VAGC up

→

gain down). If this pin is left

open, then it is default at

maximum gain.

300

Ω

3 k

Ω

ESD

44 k

Ω

To AGC Amp

IF-in1

IF-in2

Differential input pins of 1stIF

AGC amplifier.

GNDanalog

Ground pin of analog portion of

the chip.

4 k

Ω

2 k

Ω

2 k

Ω

4 k

Ω

1.42 k

Ω

1.42 k

Ω

4 k

Ω

4 k

Ω

Regulator

ESD

Data Sheet PU10282EJ01V0DS

µPB1008K

UPB1007K Datasheet(PDF) 9 Page - Renesas Technology Corp

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