PS2500 datasheet(11/28 Pages) ETC2

11 / 28 page

PS2500 2.2 GHz Fractional-N Frequency Synthesizer

- 11 -

Philsar Semiconductor Inc.

146 Colonnade Road S.

Nepean, Ontario, Canada

K2E 7Y1

Tel: 613-274-0922

Fax: 613-274-0915

www.philsar.com

PMP-001-DS2 V1.2

A shortened serial interface write where /CS is from 2 to 12 Clock cycles wide and modulation data (2 to

12 bits) is presented on the Mod_in pin. The Mod_in is the alternate pin for entering modulation data

directly in modulation data register with shortened /CS strobes. This mode is selected through the

modulation control register. This method of data entry also eliminates the register address overhead on the

serial interface and permits a different device than the one controlling the channel selection to enter the

modulation data (eg. a microcontroller for channel selection and a DSP for modulation data). All serial

interface bits are re-synchronized internally at the reference oscillator frequency and the content of the

modulation data register is passed to the modulation unit at the next falling edge of the divided main VCO

frequency (Fpd_main).

Modulation data samples in the modulation data register can be from 2 to 12 bits long, enabling the user to

select how many distinct frequency steps will be used for the desired modulation scheme.

The user can also control the frequency deviation through the Modulation Data Magnitude Offset in the

modulation control register. This permits shifting of the modulation data to accomplish a 2m multiplication

of frequency deviation

The programmable range of -0.5 to +0.5 of the main

∆Σ modulator can be exceeded up to the condition where the sum of the dividend and the

modulation data obey

-0.5625

≤ (N

mod + dividend )

≤ +0.5625

before requiring changing Ninteger.

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