PS2500 2.2 GHz Fractional-N Frequency Synthesizer
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Philsar Semiconductor Inc.
146 Colonnade Road S.
Nepean, Ontario, Canada
K2E 7Y1
Tel: 613-274-0922
Fax: 613-274-0915
www.philsar.com
PMP-001-DS2 V1.2
Values to be loaded are:
• Main Phase Detector Gain = 5-bit value for programmable main phase detector gain, Kd, of 20 to 160
µA/radian in steps of approximately 5 µA/radian. Valid range is from 4 to 31 decimal for 20 to 160
µA/radian respectively.
• Main Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the main
phase detector. When this bit is a 0, the LD/PSmain is configured to be a lock detect active low open
collector pin. When this bit is a 1, the LD/PSmain is configured to be a frequency power steering pin and
can be used to bypass the external main loop filter to provide faster frequency acquisition.
• Aux Phase Detector Gain = 5-bit value for programmable auxiliary phase detector gain, Kd, of 20 to 160
µA/radian in steps of approximately 5 µA/radian. Valid range is from 4 to 31 decimal for 20 to 160
µA/radian respectively.
• Aux Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the auxiliary
phase detector. When this bit is a 0, the LD/PSaux is configured to be a lock detect active low open
collector pin. When this bit is a 1, the LD/PSaux is configured to be a frequency power steering pin and
may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition.
Figure 11: Hex7 Power Down and Multiplexer Output Register (Write only)
This register permits control of the power-down modes, internal multiplexer output and Main
∆Σ
synthesizer fractionality.
Values to be loaded are:
• Full Power Down = 1-bit value for powering down the whole chip except for the reference oscillator and
the serial interface. When this bit is 0, the PS2500 is powered up. When this bit is 1, the PS2500 is in full
power-down mode excluding the Mux_out pin.
Full Power Down
Main Synthesizer Power Down
A3
0
1
2
3
4
5
6
7
8
9
10
11
0
A0
A1
A2
1
1
1
X
X
Main Synthesizer Mode
Main Synthesizer
∆Σ Fractionality
Auxiliary Synthesizer Power Down
Multiplexer Output Selection
Auxiliary Synthesizer Mode
Mux_out Pin Tri-State Enable
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