MP86998

– INTEGRATED INTELLI-PHASETM SOLUTION IN TLGA PACKAGE

MP86998 Rev. 1.0

www.MonolithicPower.com

12

11/3/2020

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© 2020 MPS. All Rights Reserved.

APPLICATION INFORMATION

PCB Layout Guidelines

Efficient

PCB

layout

is

critical

for

stable

operation. For the best results, refer to Figure 3

and follow the guidelines below:

1. Place the input MLCC capacitors as close to

VIN and PGND as possible.

2. Place the major MLCC capacitors on the

same layer as the MP86998.

3. Place

as

many

VIN

and

PGND

vias

underneath the package as possible.

4. Place the vias between the VIN or PGND long

pads.

5. Place a VIN copper plane on the second inner

layer

to

form

the

PCB

stack

as

positive/negative/positive, which reduces the

parasitic impedance from the input MLCC

capacitor to the MP86998. Ensure that the

copper plane on the inner layer covers the

VIN vias underneath the package, as well as

the input MLCC capacitors.

6. Place more PGND vias close to the PGND

pin/pad to minimize both thermal resistance

and parasitic resistance/impedance.

7. Place

the

BST

capacitor

and

VDRV

capacitor as close to the MP86998

’s pins as

possible.

8. Use a trace width of 20mils or longer to route

the path.

9. Avoid placing vias on the BST driving path.

10. Use a 0.1µF to 0.22µF bootstrap capacitor.

11. Place the VDD decoupling capacitor close to

the device.

12. Connect AGND and PGND at the point of the

VDD capacitor's ground connection.

13. Keep the IOUT signal trace away from high-

current paths, such as SW and PWM.

PGND

40

41

Figure 3: Example of PCB Layout (Placement and Top Layer PCB)

Input Capacitor: 0805 Package (Top and Bottom Sides) and 0402 Package (Top Side)

Inductor: 11mmx8mm Package

VDD/BST/VDRV Capacitor: 0402 Package

Via Size: 20mils/10mils