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UPD17708 Datasheet(PDF) 261 Page - Renesas Technology Corp

Part # UPD17708
Description  MOS INTEGRATED CIRCUIT
PDF  358 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD17708 Datasheet(HTML) 261 Page - Renesas Technology Corp

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259
µPD17704, 17705, 17707, 17708, 17709
Figure 17-4. Setting Division Value (N Value) of PLL Frequency Synthesizer
Note
The value of PLLSCNF flag is transferred when a write (PUT) instruction is executed to the PLL data register
(PLLR). Therefore, data must be set to the PLLSCNF flag before executing the write instruction to the PLL
data register.
Data buffer
DBF3
DBF2
Name
PLL data
register
Symbol
PLLR
Peripheral
address
42H
DBF1
DBF0
b3 b2 b1 b0
b3
b0
b0
b1
b1
b2
b2
b3
b3
b4
b4
b5
b5
b6
b6
b7
b7
b8
b8
b9
b9
b10
b10
b11
b11
b12
b12
b13
b13
b14
b14
b15
b15
b16
b6 b5 b4
b10 b9 b8 b7
b13 b12
b15 b14
b11
Peripheral register
PLL
N value data
(17 bits)
Direct division
mode
0
don't care
Setting prohibited
Division value N: N = x
Setting prohibited
Division value N: N = x
don't care
don't care
don't care
15 (00FH)
212–1 (FFFH)
Pulse swallow
mode
Transfer data
Valid data
Sets high-order 16 bits of division value
Sets least significant bit of division value Note
Name
PLL mode
selection
address
10H
b3
P
L
L
S
C
N
F
P
L
L
M
D
1
P
L
L
M
D
0
0
b2 b1 b0
Register file
GET
PUT
16
Sets division value (N value) of PLL
frequency synthesizer
x
0
1023 (3FFH)
217–1 (1FFFFH)
x
don't care
16 (010H)
1024 (400H)



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