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UPD17708 Datasheet(PDF) 262 Page - Renesas Technology Corp |
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UPD17708 Datasheet(HTML) 262 Page - Renesas Technology Corp |
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262 / 358 page  260 µPD17704, 17705, 17707, 17708, 17709 17.3 Reference Frequency Generator Figure 17-5 shows the configuration of the reference frequency generator. The reference frequency generator generates the reference frequency “fr” of the PLL frequency synthesizer by dividing the 4.5 MHz output of a crystal oscillator. Thirteen frequencies can be selected as reference frequency fr: 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 18, 20, 25, and 50 kHz. The reference frequency fr is selected by the PLL reference frequency selection register. Figure 17-6 shows the configuration and function of the PLL reference frequency selection registerion. Figure 17-5. Configuration of Reference Frequency Generator PLLRFCK3 flag PLLRFCK2 flag PLLRFCK1 flag PLLRFCK0 flag MUX 1 kHz 1.25 kHz 2.5 kHz 25 kHz 50 kHz OFF PLL disable signal To -DET Divider 4.5 MHz φ |
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