UPD720113 datasheet(5/34 Pages) RENESAS

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Data Sheet S16618EJ3V0DS

µPD720113

APLL

: Generates all clocks of Hub.

ALL_TT

: Translates the high-speed transactions (split transactions) for full/low-speed device

to full/low-speed transactions.

ALL_TT buffers the data transfer from either

upstream or downstream direction. For OUT transaction, ALL_TT buffers data from

upstream port and sends it out to the downstream facing ports after speed

conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers

data from downstream ports and sends it out to the upstream facing ports after

speed conversion from full/low-speed to high-speed.

CDR

: Data & clock recovery circuit

DPC

: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and

Resume

DP(n)_PHY

: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and

low-speed (1.5 Mbps) transaction

EP0

: Endpoint 0 controller

EP1

: Endpoint 1 controller

F_TIM (Frame Timer)

: Manages hub’s synchronization by using micro-SOF which is received at upstream

port, and generates SOF packet when full/low-speed device is attached to

downstream facing port.

FS_REP

: Full/low-speed repeater is enabled when the

µPD720113 are worked at full-speed

mode

OSB

: Oscillator Block

ROM I/F

: Interface block for external Serial ROM which contains user-defined descriptors

SERDES

: Serializer and Deserializer

SIE_2H

: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.

UP_PHY

: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)

transaction

UPC

: Upstream Port Controller handles Suspend and Resume

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