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UPD720113 Datasheet(PDF) 20 Page - Renesas Technology Corp |
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UPD720113 Datasheet(HTML) 20 Page - Renesas Technology Corp |
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20 / 34 page ![]() Data Sheet S16618EJ3V0DS 18 µPD720113 External Serial ROM Timing Parameter Symbol Condition MIN. TYP. MAX. Unit Clock frequency fSCL 94.6 100 kHz Clock pulse width low tLOW 4700 ns Clock pulse width high tHIGH 4000 ns Clock low to data out valid tAA 100 3500 ns Time the bus must be free before a new transmission can start tBUF 4700 ns Start hold time tHD.STA 4000 ns Start setup time tSU.STA 4700 ns Data in hold time tHD.DTA 0 ns Data in setup time tSU.DTA 250 ns Stop setup time tSU.STO 4700 ns Data out hold time tDH 300 ns Write cycle time tWR 15 ms Figure 2-9. External Serial ROM Bus Timing SCL SDA (Output) SDA (Input) tSU.STA tHD.STA tSU.DAT tHIGH tLOW tLOW tHD.DAT tAA tDH tSU.STO tBUF Figure 2-10. External Serial ROM Write Cycle Timing SCL SDA Word n 8th bit ACK Stop condition Start condition tWR |
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