UPD720113 datasheet(22/34 Pages) RENESAS

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Data Sheet S16618EJ3V0DS

µPD720113

(2/4)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Full-speed Electrical Characteristics (Continued)

Consecutive frame interval jitter

tRFI

No clock adjustment

Source jitter total (including frequency

tolerance) (Figure 2-15):

To next transition

For paired transitions

tDJ1

tDJ2

Note

−3.5

−4.0

+3.5

+4.0

Source jitter for differential transition to

SE0 transition (Figure 2-16)

tFDEOP

−2

Receiver jitter (Figure 2-17):

To Next Transition

For Paired Transitions

tJR1

tJR2

−18.5

−9

+18.5

Source SE0 interval of EOP (Figure 2-16)

tFEOPT

160

175

Receiver SE0 interval of EOP (Figure 2-16)

tFEOPR

Width of SE0 interval during differential

transition

tFST

Hub differential data delay (Figure 2-13)

(with cable)

(without cable)

tHDD1

tHDD2

Hub differential driver jitter (including cable)

(Figure 2-13):

To next transition

For paired transitions

tHDJ1

tHDJ2

−3

−1

Data bit width distortion after SOP (Figure

2-13)

tFSOP

−5

Hub EOP delay relative to tHDD (Figure

2-14)

tFEOPD

Hub EOP output width skew (Figure 2-14)

tFHESK

−15

+15

High-speed Electrical Characteristics

Rise time (10% to 90%)

tHSR

500

Fall time (90% to 10%)

tHSF

500

Driver waveform

See Figure 2-11.

High-speed data rate

tHSDRAT

479.760

480.240

Mbps

Microframe interval

tHSFRAM

124.9375

125.0625

µs

Consecutive microframe interval difference

tHSRFI

4 high-

speed

Bit

times

Data source jitter

See Figure 2-11.

Receiver jitter tolerance

See Figure 2-4.

Hub data delay (without cable)

tHSHDD

36 high-

speed

+4 ns

Bit

times

Hub data jitter

See Figure 2-4, Figure 2-11.

Hub delay variation range

tHSHDV

5 high-

speed

Bit

times

Note Excluding the first transition from the Idle state.

UPD720113 Datasheet(PDF) 22 Page - Renesas Technology Corp

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