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UC1682
80x104RGB CSTN Controller-Driver
Revision 0.6
9
REFERENCE COG LAYOUT
D0
D1
D2
D3
D4
D5
D6
VDDX
D7
COM_pad<80>
COM_pad<78>
COM_pad<52>
COM_pad<50>
SEG_pad<312>
SEG_pad<311>
VSS2
VSS2
VSS2
VSS
VSS
VSS
VSS
VSS
VSS
PRG1
PRG2
PRG3
TST1
TST2
TST3
TST4
TST4
BM1
VDDX
BM0
WR1
VDDX
WR0
CD
CS0
VDDX
CS1
RST_
VREF
ID
VB1P
VB1P
VB1P
VB1P
VB1P
VB0P_S
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VB0P
VDD
VDD
VDD
VDD
VDD
VDD
VDD2
VDD2
VDD2
VDD2
VDD2
VDD3
VDD3
VDD3
VDD3
VSS2
VSS2
SEG_pad<196>
SEG_pad<195>
SEG_pad<194>
VLCDOUT
VLCDOUT
VLCDIN
VLCDIN
VB0N_S
VB0N
VB0N
VB0N
VB0N
VB0N
VB0N
VB0N
VB0N
VB0N
VB1N_S
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1N
VB1P_S
VB1P
VB1P
VB1P
VB1P
COM_pad<49>
COM_pad<51>
COM_pad<77>
COM_pad<79>
SEG_pad<62>
SEG_pad<61>
SEG_pad<60>
SEG_pad<59>
SEG_pad<2>
SEG_pad<1>
D7
D6
D5
D4
D3
D2
D1
D0
RST
CS0
WR1
TST4
VSS ~ VSS2
VSS ~ VSS2
VSS ~ VSS2
VDD ~ VDD3
VDD ~ VDD3
VDD ~ VDD3
VDD ~ VDD3
VDD ~ VDD3
VB0+ ~ SB0+
CD
WR0
VB0+ ~ SB0+
VB0+ ~ SB0+
VB1+ ~ SB1+
VB1+ ~ SB1+
VB1+ ~ SB1+
VB1- ~ SB1-
VB1- ~ SB1-
VB1- ~ SB1-
VB1- ~ SB1-
VB0- ~ SB0-
VB0- ~ SB0-
VB0- ~ SB0-
VB0- ~ SB0-
VLCD
VLCD
NC
NC
VSS ~ VSS2
VSS ~ VSS2
Notes for VDD with COG:
The VDD=1.8V-typ operation condition of UC1682 should be met under all LCM formats. Unless VDD, VDD2/3
ITO trances can each be controlled to be 5 Ω or lower, otherwise VDD-VDD2/3 separation can cause the actual
on-chip VDD to drop below VDD=1.7V during high speed data write condition. Therefore, for COG, VDD-VDD2/3
separation is not suitable for pure ITO based COG designs.
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