UC1682
80x104RGB CSTN Controller-Driver
Revision 0.6
33
INPUT COLOR FORMATS
UC1682 supports the following four different input
color formats.
256C (8-bit/RGB): This is the most compact
color mode, and is intended to minimize the bus
cycle required to refresh the display buffer. On-
chip extension circuit will automatically expand
the input RGB data into on-chip RAM buffer
format.
4KC (12-bit/RGB): In this color mode, G will be
extended while B will be dithered, and the input
data will be converted into 4R-5G-3B format
before they are stored to display RAM.
56KC (16-bit/RGB): On-chip dither engine will
convert the input data into internal 12-bit-per-
RGB pixel format and store it to on-chip display
RAM. This is the default mode.
221KC (24-bit/RGB): On-chip dither engine will
convert input data into 4R-5G-3B format and
store it to on-chip display RAM. This mode
provides the smoothest shades and the most
vivid color in the LCD.
Changing color mode does not affect the content
already stored in the display buffer RAM. Users
can use several color modes together in real time.
For example, the menu portion can be painted in
256-color mode for fast update speed, and then
switch to 221K-color mode, together with window
programming option, and take advantage of built-
in dither engine to produce smooth graphics
images.
LAYOUT CONSIDERATIONS FOR COM SIGNALS
Since the COM scanning pulse of UC1682 can
be as short as 30µS, it is critical to control the RC
delay of COM signal to minimize distortion of
COM scanning pulse.
For the best image quality, limit the worst case of
RC delay of COM signal as calculated below.
(RROW / 2.7+ RCOM + ROUT) x CROW < 2µS
where
CROW:
LCD loading capacitance of one
row of pixels. It can be calculated
by CLCD/Mux-Rate, where CLCD is
the LCD panel capacitance.
RROW:
ITO resistance over one row of
pixels within the active area
RCOM:
COM routing resistance from IC to
the active area
ROUT:
COM output impedance
In addition, please make sure
| RCMAX – RCMIN | < 0.3 x RCMAX
so that the COM distortions on the top of the
screen to the bottom of the screen are uniform.
LAYOUT CONSIDERATIONS FOR SEG SIGNALS
Excessive SEG signal RC decay can cause
image dependent changes of medium gray
shades and sharply increase of SEG direction
crosstalk.
Please limit the worst case of SEG signal RC
delay as calculated below.
(RCOL /2.7 + RSEG) x CCOL < 0.5µS
where
CCOL:
LCD loading capacitance of one
pixel column. It can be calculated
by CLCD / #_of column, CLCD is the
LCD panel capacitance.
RCOL:
ITO resistance over one column of
pixels within the active area
RSEG:
SEG routing resistance from IC to
the active area + SEG driver
output impedance
LAYOUT CONSIDERATIONS FOR SEG SIGNALS
Excessive SEG signal RC decay can cause
image dependent changes of medium gray
shades and sharply increase of SEG direction
crosstalk.
For good image quality, please limit the worst
case of SEG signal RC delay as calculated below.
(RCOL /2.7 + RSEG) x CCOL < 0.4µS
where
CCOL:
LCD loading capacitance of one
pixel column. It can be calculated
by CLCD / #_of column, CLCD is the
LCD panel capacitance.
RCOL:
ITO resistance over one column of
pixels within the active area
RSEG:
SEG routing resistance from IC to the
active area + SEG driver output impedance
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