ULTRACHIP
High-Voltage Mixed-Signal IC
© 1999 ~ 2003
6
ES Specifications
Name
Type
Pins
Description
HOST INTERFACE
BM0
BM1
I
Bus mode: The interface bus mode is determined by BM[1:0] and D[7:6]
by the following relationship:
BM[1:0]
D[7:6]
Mode
11
Data
6800/8-bit
10
Data
8080/8-bit
01
0X
6800/4-bit
00
0X
8080/4-bit
01
10
3-wire SPI w/ 9-bit token
(S9: conventional)
00
10
4-wire SPI w/ 8-bit token
(S8: conventional)
00
11
3/4-wire SPI w/ 8-bit token
(S8uc: Ultra-Compact)
CS1
CS0
I
2
Chip Select. Chip is selected when CS1=”H” and CS0 = “L”. When the
chip is not selected, D[7:0] will be high impedance.
RST
I
When RST=”L”, all control registers are re-initialized by their default states.
Since UC1682 has built-in Power-ON Reset and Software Reset
command, RST pin is not required for proper chip operation.
An RC Filter has been included on-chip. There is no need for external RC
noise filter. When RST is not used, connect the pin to VDD.
CD
I
Select Control data or Display data for read/write operation. In S9 modes,
CD pin is not used. Connect CD to VSS when not used.
”L”: Control data
”H”: Display data
ID
I
ID pin is for production control. The connection will affect the content of
D[7] when using Get Status command. Connect to VDD for “H” or VSS for
“L”.
WR0
WR1
I
WR[1:0] controls the read/write operation of the host interface. See Host
Interface section for more detail.
In parallel mode, WR[1:0] meaning depends on whether the interface is in
the 6800 mode or the 8080 mode. In serial interface modes, these two
pins are not used, connect them to VSS.
D0~D7
I/O
Bi-directional bus for both serial and parallel host interfaces.
In serial modes, connect D[0] to SCK, D[3] to SDA,
BM=1x
(Parallel)
BM=0x
(Parallel)
BM=01
(S9)
BM=00
(S8/S8uc)
D0
D0
D0/D4
SCK
SCK
D1
D1
D1/D5
–
–
D2
D2
D2/D6
–
–
D3
D3
D3/D7
SDA
SDA
D4
D4
–
–
–
D5
D5
–
–
–
D6
D6
–
0
S8/S8uc
D7
D7
0
1
1
Connect unused pins to VSS.
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