UC1682THCZ datasheet(39/70 Pages) ETC2

39 / 70 page

UC1682

80x104RGB CSTN Controller-Driver

Revision 0.6

S8UC (3/4-WIRE) INTERFACE

Only write operations are supported in this 3/4-wire

serial mode. The data format is identical to S8.

However, in addition to CS pins, CD pin transitions

will also reset the bus cycle in this mode. So, if CS

pins are hardwired to enable chip-select, the bus

can work properly with only three signal pins.

S9 (3-WIRE) INTERFACE

Only write operations are supported in this 3-wire

serial mode. Pin CS[1-0] are used for chip select

and bus cycle reset. On each write cycle, the first

bit is CD, which determines the content of the

following 8 bits of data, MSB first. These 8

command or data bits are latched on rising SCK

edges into an 8-bit data holder. If CD=0, the data

byte will be decoded as command. If CD=1, this 8-

bit will be treated as data and transferred to proper

address in the Display Data RAM at the rising edge

of the last SCK pulse.

By sending CD information explicitly in the bit

stream, control pin CD is not used, and should be

connected to either VDD or VSS. The toggle of CS0

or CS1 for each byte of data/command is

recommended but optional.

CS0

SDA

SCK

FIGURE 7.c: 3-wire Serial Interface (S9)

UC1682THCZ Datasheet(PDF) 39 Page - List of Unclassifed Manufacturers