UC1682THCZ datasheet(38/70 Pages) ETC2

38 / 70 page

ULTRACHIP

High-Voltage Mixed-Signal IC

ES Specifications

LLSB

DL+K

CMSB

CLSB

Dummy

DC+1

MMSB

MLSB

L+K

L+K+1

C+1

C+2

C+3

DL+K

Dummy

DC+1

DC+2

External

___

D[7:0]

Internal

Write

Read

Data

Latch

Column

Address

FIGURE 6: 8 bit Parallel Interface & Related Internal Signals

SERIAL INTERFACE

UC1682 supports three serial modes, one 4-wire

SPI mode (S8), one compact 3/4-wire mode (S8uc)

and one 3-wire SPI mode (S9). Bus interface mode

is determined by the wiring of the BM[1:0] and

D[7:6]. See table in last page for more detail.

S8 (4-WIRE) INTERFACE

Only write operations are supported in 4-wire serial

mode. Pin CS[1:0] are used for chip select and bus

cycle reset. Pin CD is used to determine the

content of the data been transferred. During each

write cycle, 8 bits of data, MSB first, are latched on

eight rising SCK edges into an 8-bit data holder.

If CD=0, the data byte will be decoded as

command. If CD=1, this 8-bit will be treated as data

and transferred to proper address in the Display

Data RAM on the rising edge of the last SCK pulse.

Pin CD is examined when SCK is pulled low for the

LSB (D0) of each token.

CS0

SDA

SCK

FIGURE 7.a: 4-wire Serial Interface (S8)

CS0

SDA

SCK

FIGURE 7.b: 3/4-wire Serial Interface (S8uc)

UC1682THCZ Datasheet(PDF) 38 Page - List of Unclassifed Manufacturers

UC1682THCZ Datasheet(HTML) 38 Page - List of Unclassifed Manufacturers

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