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ES9820 Datasheet(PDF) 42 Page - ESS Technology,Inc |
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ES9820 Datasheet(HTML) 42 Page - ESS Technology,Inc |
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42 / 117 page  CONFIDENTIAL ADVANCE INFORMATION 0.3 ES9820 Product Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 42 Addr (Hex) Addr (Dec) Register 7 6 5 4 3 2 1 0 0x0 0 SYS CONFIG SOFT_RESET OUTPUT_SEL RESERVED ENABLE_2X _MODE RESERVED MONO_MODE RESERVED 0x1 1 ADC CLOCK CONFIG1 RESERVED ENABLE_DATA_ IN_CH2 ENABLE_DA TA_IN_CH1 RESERVED ENABLE_ADC_CH2 ENABLE_ADC_CH1 0x2 2 ADC CLOCK CONFIG2 RESERVED SELECT_ADC_H ALF SELECT_ADC_NUM 0x3 3 ADC CLOCK CONFIG3 OUTPUT2_SEL FORCE_OUTPU T2 INVERT_FIR ST_CLK_SA MPLE2 SELECT_IA DC_HALF SELECT_IADC_NUM 0x4 4 ADC CLOCK CONFIG4 FORCE_PHAS E_CLK_IADC PHASE_CLK_IADC RESERVED INVERT_SAMPLE_C LOCK_CH2 INVERT_SAMPLE_CLOCK_CH1 0x5 5 SPDIF CONFIG RESERVED ENABLE_SPDIF_C LK RESERVED 0x6 6 DSD CONFIG RESERVED DSD_DDR DSD_MAST ER_MODE RESERVED ENABLE_DSD_CLK_ CH2 ENABLE_DSD_CLK_CH1 0x7 7 DSD AND I2S/TDM MASTER CLK CONFIG MASTER_WS_SCALE DSD_CLK_D IV2 SELECT_DSD_NUM 0x8 8 I2S/TDM MASTER MODE CONFIG MASTER_BCK_ DIV1 MASTER_W S_IDLE MASTER_FRAME_LENGTH MASTER_W S_PULSE_M ODE MASTER_BCK_IN VERT MASTER_WS_INVE RT MASTER_MODE_ENABLE 0x9 9 I2S/TDM MASTER CLK CONFIG SELECT_I2S_T DM_HALF SELECT_I2S_TDM_NUM 0xA 10 TDM CONFIG1 TDM_BIT_DELAY TDM_VALID_EDG E TDM_LJ ENABLE_TDM_CLK 0xB 11 TDM CONFIG2 TDM_GPIO456 TDM_CASC ADE TDM_LENGTH TDM_CH_NUM 0xC 12 TDM SLOT CONFIG CH1 RESERVED TDM_LINE_SEL_CH1 TDM_SLOT_SEL_CH1 0xD 13 TDM SLOT CONFIG CH2 RESERVED TDM_LINE_SEL_CH2 TDM_SLOT_SEL_CH2 0xE- 0x11 14-17 RESERVED RESERVED 0x12 18 PCM DATA OUTPUT MAPPING RESERVED OUTPUT_MAPPING_CH2 OUTPUT_MAPPING_CH1 0x13 19 DSD DATA OUTPUT MAPPING RESERVED DSD_MAPPING_CH2 DSD_MAPPING_CH1 0x14 20 TPDF DITHER LEVEL RESERVED DITHER_SCALE 0x15 21 DITHER MASK DITHER_MASK 0x16 22 DITHER MASK DITHER_MASK 0x17 23 FS GEN PHASE CONTROL DSD_SYNC_T O_1FS FS_PHASE 0x18- 0x1A 24-26 RESERVED RESERVED 0x1B 27 INTERRUPT RESERVED INTERRUPT_CL EAR_CH2_CLIP _DETECTION INTERRUPT _CLEAR_CH 1_CLIP_DET ECTION RESERVED INTERRUPT_MASK_ CH2_CLIP_DETECTI ON INTERRUPT_MASK_CH1_CLIP_ DETECTION 0x1F- 0x20 32-28 SPDIF CONFIG SPDIF_CS 0x21 33 DSD DITHER SCALE AND SYNC CONTROL SYNC_POSED GE_FRAME DISABLE_S YNC_REF FORCE_FIR_SY NC DSD_DITHER_SCALE 0x22 34 SYNC CONTROL AUTO_ADC_CL KDIV_SYNC AUTO_CLK_ IADC_PHAS E_SYNC AUTO_DSD_PH ASE_SYNC AUTO_WS_ PHASE_SYN C AUTO_ICG_ EN_SYNC AUTO_ICG_SYNC AUTO_FIR_SYNC AUTO_FS_SYNC 0x23 35 ASP1 CONFIG RESERVED SELECT_ASP1_NUM ENABLE_ASP1_CLK 0x24 36 ASP2 CONFIG RESERVED SELECT_ASP2_NUM ENABLE_ASP2_CLK 0x25 37 ASP ENABLE AND PROGRAMMING CONTROL ASP2_COEFF_ WE ASP1_COEF F_WE ASP2_PROGRA M_WE ASP1_PRO GRAM_WE ASP2_PRO GRAM_EN ASP1_PROGRAM _EN ENABLE_ASP2 ENABLE_ASP1 0x26 38 ASP PROGRAM ADDR ASP_PROGRAM_ADDR |
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