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ES9820 Datasheet(PDF) 10 Page - ESS Technology,Inc |
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ES9820 Datasheet(HTML) 10 Page - ESS Technology,Inc |
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10 / 117 page  CONFIDENTIAL ADVANCE INFORMATION 0.3 ES9820 Product Datasheet ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM 10 I2S decoder and Programmable Delay The ES9820 has a build in I2S decoder that can be mixed with the ASP. A programmable delay is also included to help with phase correction when mixing. I2S Decoder Configuration Registers: • Registers 59-60: I2S DECODER CONFIG Programmable Delay Registers: • Register 62-61 [9]: ENABLE_CLK_DL • Registers 62-61 [8:0]: PROG_DELAY_LINE Configuration pins for I2S decoder: • GPIO 1: BCK • GPIO 2: WS • GPIO 5: DATA (would be configured as an AUX Input through the GPIO configuration) Mixing is accomplished using the ASP registers expanded on under the Audio Signal Processor (ASP) section. Clip Detection If the peak level of the ES9820 device’s input audio stream rises above the programmed ADC#_CLIP_LEVEL value, the corresponding clip flag will be set. The clip flag will stay set until it is cleared with INTERRUPT_CLEAR_CH#_CLIP_DETECTION. Any of the GPIO pins can be configured to output the state of any of the clip flags if INTERRUPT_MASK_CH#_CLIP_ DETECTION is set for the corresponding channel. Clipping Level Registers: • Register 106: ADC CH1 PEAK DETECTOR LEVEL • Register 123: ADC CH2 PEAK DETECTOR LEVEL Clipping Interrupt Clear Registers: • Register 27 [5]: INTERRUPT_CLEAR_CH2_CLIP_DETECTION • Register 27 [4]: INTERRUPT_CLEAR_CH1_CLIP_DETECTION Clipping Interrupt Mask Registers • Register 27 [1]: INTERRUPT_MASK_CH2_CLIP_DETECTION • Register 27 [0]: INTERRUPT_MASK_CH1_CLIP_DETECTION The GPIO READBACK register values 4’d4 – 4’d5 output the clip interrupt state for CH1 & CH2, respectively. The corresponding channel bit in Register 27[3:0] INTERRUPT_CLEAR_CH#_CLIP_DETECTION needs to be set for the GPIO to output the flag value. |
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