7 Detailed Description

7.1 Overview

The LM2104 is a high-voltage gate driver designed to drive both the high-side and the low-side N-channel

FETs in a synchronous buck or a half-bridge configuration. The two outputs are controlled with a single TTL-

compatible input PWM signal provided at the IN pin, and a TTL-compatible shutdown signal provided at the SD

pin. The device can also work with CMOS type control signals at its inputs as long as the signals meet the

turn-on and turn-off threshold specifications of the LM2104. The floating high-side driver is capable of working

with a recommended BST voltage up to 105 V. A robust level shifter operates at high speed while consuming

low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage

lockout (UVLO) is provided on both the low-side and the high-side power rails.

7.2 Functional Block Diagram

LEVEL

SHIFT

UVLO

UVLO

IN

SD

GVDD

BST

GH

SH

GL

GND

DRIVER

STAGE

DRIVER

STAGE

Dead-time

block and

cross

conduction

prevention

logic

GVDD

7.3 Feature Description

7.3.1 Start-Up and UVLO

Both the high-side and the low-side driver stages include UVLO protection circuitry which monitors the supply

voltage (VGVDD) and the bootstrap capacitor voltage (VBST-SH). The UVLO circuit inhibits each output until

sufficient supply voltage is available to turn on the external MOSFETs, and the built-in UVLO hysteresis prevents

chattering during supply voltage variations. When the supply voltage is applied to the GVDD pin of the device,

both outputs are held low until VGVDD exceeds the UVLO threshold, typically 8 V. Any UVLO condition on the

bootstrap capacitor (VBST–SH) disables only the high-side output (GH).

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LM2104

SNVSCH8A – SEPTEMBER 2023 – REVISED OCTOBER 2023

Copyright © 2023 Texas Instruments Incorporated

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Product Folder Links: LM2104